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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. BQ25710 slusd20 ? july 2018 BQ25710 smbus narrow vdc buck-boost battery charge controller with system power monitor and processor hot monitor 1 1 features 1 ? pin-to-pin and software compatible to bq25700a ? charge 1s to 4s battery from wide range of input source ? 3.5-v to 24-v input operating voltage ? supports usb2.0, usb 3.0, usb 3.1 (type c), and usb power delivery (usb-pd) input current settings ? seamless transition among buck, buck-boost and boost operations ? input current and voltage regulation (idpm and vdpm) against source overload ? power/current monitor for cpu throttling ? comprehensive prochot profile, imvp8/imvp9 compliant ? input and battery current monitor ? system power monitor, imvp8/imvp9 compliant ? narrow-vdc (nvdc) power path management ? instant-on with no battery or depleted battery ? battery supplements system when adapter is fully-loaded ? battery mosfet ideal diode operation in supplement mode ? power up usb port from battery (usb otg) ? 3-v to 20.8-v votg with 8 mv resolution ? output current limit up to 6.4 a with 50 ma resolution ? pass through mode (ptm) for system power efficiency improvement ? when system is powered by battery only, vmin active protection (vap) mode supplements battery from input capacitors during system peak power spike ? input current optimizer (ico) to extract max input power ? 800-khz or 1.2-mhz programmable switching frequency for 2.2- h or 1.0- h inductor ? host control interface for flexible system configuration ? smbus (BQ25710) port optimal system performance and status reporting ? hardware pin to set input current limit without ec control ? integrated adc to monitor voltage, current and power ? high accuracy for the regulation and monitor ? 0.5% charge voltage regulation ? 2% input/charge current regulation ? 2% input/charge current monitor ? 4% power monitor ? safety ? thermal shutdown ? input, system, battery overvoltage protection ? input, mosfet, inductor overcurrent protection ? low battery quiescent current ? package: 32-pin 4 4 wqfn 2 applications ? ultra-books, notebooks, detachable, tablet pcs and power bank ? industrial and medical equipment ? portable equipment with rechargeable batteries 3 description this device is a synchronous nvdc buck-boost battery charge controller, offering a low component count, high efficiency solution for space constrained, 1s-4s battery charging applications. device information (1) part number package body size (nom) BQ25710 wqfn (32) 4.00 mm 4.00 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. application diagram productfolder BQ25710 acn vbus hidrv1 srn vsys batt (1s-4s) btst1btst2 lodrv1 sw1 sw2 lodrv2 hidrv2 srp batdrv acp sys host q1 q2 q3 q4 adapter 3.5v 24v smbus iadpt, ibat, psys, prochot support &community tools & software technical documents ordernow
2 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 description (continued) ......................................... 3 6 device comparison table ..................................... 4 7 pin configuration and functions ......................... 5 8 specifications ......................................................... 8 8.1 absolute maximum ratings ...................................... 8 8.2 esd ratings .............................................................. 8 8.3 recommended operating conditions ....................... 8 8.4 thermal information .................................................. 9 8.5 electrical characteristics ........................................... 9 8.6 timing requirements .............................................. 17 8.7 typical characteristics ............................................ 18 9 detailed description ............................................ 21 9.1 overview ................................................................. 21 9.2 functional block diagram ....................................... 22 9.3 feature description ................................................. 23 9.4 device functional modes ........................................ 29 9.5 programming ........................................................... 30 9.6 register map ........................................................... 33 10 application and implementation ........................ 69 10.1 application information .......................................... 69 10.2 typical application ................................................ 69 11 power supply recommendations ..................... 76 12 layout ................................................................... 77 12.1 layout guidelines ................................................. 77 12.2 layout example .................................................... 77 13 device and documentation support ................. 79 13.1 device support .................................................... 79 13.2 documentation support ....................................... 79 13.3 receiving notification of documentation updates 79 13.4 community resources .......................................... 79 13.5 trademarks ........................................................... 79 13.6 electrostatic discharge caution ............................ 79 13.7 glossary ................................................................ 79 14 mechanical, packaging, and orderable information ........................................................... 80 4 revision history date revision notes july 2018 * initial release.
3 BQ25710 www.ti.com slusd20 ? july 2018 product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated 5 description (continued) the nvdc configuration allows the system to be regulated at battery voltage, but not drop below system minimum voltage. the system keeps operating even when the battery is completely discharged or removed. when load power exceeds input source rating, the battery goes into supplement mode and prevents the system from crashing. BQ25710 charges battery from a wide range of input sources including usb adapter, high voltage usb pd sources and traditional adapters. during power up, the charger sets converter to buck, boost or buck-boost configuration based on input source and battery conditions. the charger automatically transits among buck, boost and buck-boost configuration without host control. in the absence of an input source, BQ25710 supports usb on-the-go (otg) function from 1- to 4-cell battery to generate adjustable 3 v to 20.8 v on vbus with 8 mv resolution. the otg output voltage transition slew rate can be configurable, which is complied with the usb pd 3.0 pps specifications. when only battery powers the system and no external load is connected to the usb otg port, BQ25710 supports the vmin active protection (vap) feature, in which the device charges up the vbus voltage from the battery to store some energy in the input decoupling capacitors. during the system peak power spike, the huge current drawing from the battery creates a larger voltage drop across the impedance from the battery to the system. the energy stored in the input capacitors will supplement the system, to prevent the system voltage from dropping below the minimum system voltage and causing the system crash. this vmin active protection (vap) is designed to absorb system power peaks during periods of soc high power demand, which is highly recommended by intel for the platforms with 1s~2s battery. BQ25710 monitors adapter current, battery current and system power. the flexibly programmed prochot output goes directly to cpu for throttle back when needed.
4 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated 6 device comparison table bq25700a bq25703a bq25708 BQ25710 bq25713 bq25713b interface smbus i2c smbus smbus i2c i2c device address 09h 6bh 09h 09h 6bh 6ah vap for imvp9 no no no yes yes yes pass through mode no no no yes yes yes otg mode yes yes no yes yes yes otg voltage range 4.48v-20.8v 4.48v-20.8v n/a 3.0v-20.8v 3.0v-20.8v 3.0v-20.8v otg voltage resolution 64mv 64mv n/a 8mv 8mv 8mv charging voltage resolution 16mv 16mv 16mv 8mv 8mv 8mv
5 BQ25710 www.ti.com slusd20 ? july 2018 product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated 7 pin configuration and functions rsn package 32-pin wqfn top view pin functions pin i/o description name number acn 2 pwr input current sense resistor negative input. the leakage on acp and acn are matched. a r- c low-pass filter is required to be placed between the sense resistor and the acn pin to suppress the high frequency noise in the input current signal. refer to application and implementation for acp/acn filter design. acp 3 pwr input current sense resistor positive input. the leakage on acp and acn are matched. a r- c low-pass filter is required to be placed between the sense resistor and the acp pin to suppress the high frequency noise in the input current signal. refer to application and implementation for acp/acn filter design. batdrv 21 o p-channel battery fet (batfet) gate driver output. it is shorted to vsys to turn off the batfet. it goes 10 v below vsys to fully turn on batfet. batfet is in linear mode to regulate vsys at minimum system voltage when battery is depleted. batfet is fully on during fast charge and works as an ideal-diode in supplement mode. btst1 30 pwr buck mode high side power mosfet driver power supply. connect a 0.047- f capacitor between sw1 and btst1. the bootstrap diode between regn and btst1 is integrated. btst2 25 pwr boost mode high side power mosfet driver power supply. connect a 0.047- f capacitor between sw2 and btst2. the bootstrap diode between regn and btst2 is integrated. cell_batpresz 18 i battery cell selection pin for 1 ? 4 cell battery setting. cell_batpresz pin is biased from vdda. cell_batpresz pin also sets sysovp thresholds to 5 v for 1-cell, 12 v for 2-cell, and 19.5 v for 3-cell/4-cell. cell_batpresz pin is pulled below v cell_batpresz_fall to indicate battery removal. the device exits learn mode, and disables charge. the charge voltage register reg0x 15() goes back to default. 32 sw1 9 ibat 1 vbus 24 hidrv2 31 hidrv1 10 psys 2 acn 23 sw2 30 btst1 11 prochot 3 acp 22 vsys 29 lodrv1 12 sda 4 chrg_ok 21 batdrv 28 regn 13 scl 5 otg/vap 20 srp 27 pgnd 14 cmpin 6 ilim_hiz 19 srn 26 lodrv2 15 cmpout 7 vdda 18 cell_batpresz 25 btst2 16 comp1 8 iadpt 17 comp2 thermal pad
6 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated pin functions (continued) pin i/o description name number chrg_ok 4 o open drain active high indicator to inform the system good power source is connected to the charger input. connect to the pullup rail via 10-k resistor. when vbus rises above 3.5v or falls below 24.5v, chrg_ok is high after 50ms deglitch time. when vbus falls below 3.2 v or rises above 26 v, chrg_ok is low. when any fault occurs, chrg_ok is asserted low. cmpin 14 i input of independent comparator. the independent comparator compares the voltage sensed on cmpin pin with internal reference, and its output is on cmpout pin. internal reference, output polarity and deglitch time is selectable by the smbus host. with polarity high (reg0x30[6] = 1), place a resistor between cmpin and cmpout to program hysteresis. with polarity low (reg0x30[6] = 0), the internal hysteresis is 100 mv. if the independent comparator is not in use, tie cmpin to ground. cmpout 15 o open-drain output of independent comparator. place pullup resistor from cmpout to pullup supply rail. internal reference, output polarity and deglitch time are selectable by the smbus host. comp2 17 i buck boost converter compensation pin 2. refer to bq2571x evm schematic for comp2 pin rc network. comp1 16 i buck boost converter compensation pin 1. refer to bq2571x evm schematic for comp1 pin rc network. otg/vap 5 i active high to enable otg or vap modes. when reg0x 32[5]=1, pulling high otg/vap pin and setting reg0x 32[12]=1 can enable otg mode. when reg0x 32[5]=0, pulling high otg/vap pin is to enable vap mode. hidrv1 31 o buck mode high side power mosfet (q1) driver. connect to high side n-channel mosfet gate. hidrv2 24 o boost mode high side power mosfet(q4) driver. connect to high side n-channel mosfet gate. iadpt 8 o the adapter current monitoring output pin. v (iadpt) = 20 or 40 (v (acp) ? v (acn) ) with ratio selectable in reg 0x12[4]. place a resistor from the iadpt pin to ground corresponding to the inductance in use. for a 2.2 h inductance, the resistor is 137 k . place a 100-pf or less ceramic decoupling capacitor from iadpt pin to ground. iadpt output voltage is clamped below 3.3 v. ibat 9 o the battery current monitoring output pin. v (ibat) = 8 or 16 (v (srp) ? v (srn) ) for charge current, or v (ibat) = 8 or 16 (v (srn) ? v (srp) ) for discharge current, with ratio selectable in reg 0x12[3]. place a 100-pf or less ceramic decoupling capacitor from ibat pin to ground. this pin can be floating if not in use. its output voltage is clamped below 3.3 v. ilim_hiz 6 i input current limit setting pin. program ilim_hiz voltage by connecting a resistor divider from supply rail to ilim_hiz pin to ground. the pin voltage is calculated as: v (ilim_hiz) = 1 v + 40 idpm rac, in which idpm is the target input current. the input current limit used by the charger is the lower setting of ilim_hiz pin and reg0x3f(). when the pin voltage is below 0.4 v, the device enters hi-z mode with low quiescent current. when the pin voltage is above 0.8 v, the device is out of hi-z mode. lodrv1 29 o buck mode low side power mosfet (q2) driver. connect to low side n-channel mosfet gate. lodrv2 26 o boost mode low side power mosfet (q3) driver. connect to low side n-channel mosfet gate. pgnd 27 gnd device power ground. prochot 11 o active low open drain output of processor hot indicator. it monitors adapter input current, battery discharge current, and system voltage. after any event in the prochot profile is triggered, a pulse is asserted. the minimum pulse width is adjustable in reg 0x21[14:11]. psys 10 o current mode system power monitor. the output current is proportional to the total power from the adapter and the battery. the gain is selectable through smbus. place a resistor from psys to ground to generate output voltage. this pin can be floating if not in use. its output voltage is clamped below 3.3 v. place a capacitor in parallel with the resistor for filtering. regn 28 pwr 6-v linear regulator output supplied from vbus or vsys. the ldo is active when vbus above v vbus_conven . connect a 2.2- or 3.3- f ceramic capacitor from regn to power ground. regn pin output is for power stage gate drive. scl 13 i smbus clock input. connect to clock line from the host controller or smart battery. connect a 10-k pullup resistor according to smbus specifications.
7 BQ25710 www.ti.com slusd20 ? july 2018 product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated pin functions (continued) pin i/o description name number sda 12 i/o smbus open-drain data i/o. connect to data line from the host controller or smart battery. connect a 10-k pullup resistor according to smbus specifications. srn 19 pwr charge current sense resistor negative input. srn pin is for battery voltage sensing as well. connect srn pin with optional 0.1- f ceramic capacitor to gnd for common-mode filtering. connect a 0.1- f ceramic capacitor from srp to srn to provide differential mode filtering. the leakage current on srp and srn are matched. srp 20 pwr charge current sense resistor positive input. connect srp pin with optional 0.1-uf ceramic capacitor to gnd for common-mode filtering. connect a 0.1- f ceramic capacitor from srp to srn to provide differential mode filtering. the leakage current on srp and srn are matched. sw1 32 pwr buck mode high side power mosfet driver source. connect to the source of the high side n-channel mosfet. sw2 23 pwr boost mode high side power mosfet driver source. connect to the source of the high side n-channel mosfet. vbus 1 pwr charger input voltage. an input low pass filter of 1 and 0.47 f (minimum) is recommended. vdda 7 pwr internal reference bias pin. connect a 10- resistor from regn to vdda and a 1- f ceramic capacitor from vdda to power ground. vsys 22 pwr charger system voltage sensing. the system voltage regulation limit is programmed in reg0x15() and reg0x3e(). thermal pad ? ? exposed pad beneath the ic. always solder thermal pad to the board, and have vias on the thermal pad plane connecting to power ground planes. it serves as a thermal pad to dissipate the heat.
8 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltages are with respect to gnd if not specified. currents are positive into, negative out of the specified terminal. consult packaging section of the data book for thermal limitations and considerations of packages. 8 specifications 8.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) (2) min max unit voltage srn, srp, acn, acp, vbus, vsys ? 0.3 30 v sw1, sw2 ? 2 30 btst1, btst2, hidrv1, hidrv2, /batdrv ? 0.3 36 lodrv1, lodrv2 (25ns) ? 4 7 hidrv1, hidrv2 (25ns) ? 4 36 sw1, sw2 (25ns) ? 4 30 sda, scl, regn, psys, chrg_ok, otg/vap cell_batpresz, ilim_hiz, lodrv1, lodrv2, vdda, comp1, comp2, cmpin, cmpout ? 0.3 7 /prochot ? 0.3 5.5 iadpt, ibat, psys ? 0.3 3.6 differential voltage btst1-sw1, btst2-sw2, hidrv1-sw1, hidrv2-sw2 ? 0.3 7 v srp-srn, acp-acn ? 0.5 0.5 temperature junction temperature range, t j ? 40 155 c storage temperature, t stg ? 40 155 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 8.2 esd ratings value unit v (esd) electrostatic discharge human body model (hbm), per ansi/esda/jedec js-001, allpins (1) 2000 v charged device model (cdm), per jedec specificationjesd22-c101, all pins (2) 500 8.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min max unit voltage acn, acp, vbus 0 24 v srn, srp, vsys 0 19.2 sw1, sw2 ? 2 24 btst1, btst2, hidrv1, hidrv2, /batdrv 0 30 sda, scl, regn, psys, chrg_ok, cell_batpresz, ilim_hiz, lodrv1, lodrv2, vdda, comp1, comp2, cmpin, cmpout 0 6.5 /prochot 0 5.3 iadpt, ibat, psys 0 3.3 differential voltage btst1-sw1, btst2-sw2, hidrv1-sw1, hidrv2-sw2 0 6.5 v srp-srn, acp-acn ? 0.5 0.5 junction temperature range, t j ? 20 125 c operating free-air temperature range, t j ? 40 85 c
9 BQ25710 www.ti.com slusd20 ? july 2018 product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 8.4 thermal information thermal metric (1) BQ25710 unit rsn (wqfn) 32 pins r ja junction-to-ambient thermal resistance 37.2 c/w r jc(top) junction-to-case (top) thermal resistance 26.1 c/w r jb junction-to-board thermal resistance 7.8 c/w jt junction-to-top characterization parameter 0.3 c/w y jb junction-to-board characterization parameter 7.8 c/w r jc(bot) junction-to-case (bottom) thermal resistance 2.3 c/w 8.5 electrical characteristics over t j = -40 c to 125 c (unless otherwise noted) parameter test conditions min typ max unit v #b#input _op input voltage operating range 3.5 26 v regulation accuracy max system voltage regulation v sysmax _rng system voltage regulation, measured on v sys (charge disabled) 1.024 19.2 v v sysmax _acc system voltage regulation accuracy (charge disabled) reg0x 15() = 0x41a0h (16.800 v) v srn + 160 mv v ? 2% 2% reg0x 15() = 0x3138h (12.600 v) v srn + 160 mv v ? 2% 2% reg0x 15() = 0x20d0h (8.400 v) v srn + 160 mv v ? 3% 3% reg0x 15() = 0x1068h (4.200 v) v srn + 160 mv v ? 3% 3% minimum system voltage regulation v sysmin_ rng system voltage regulation, measured on v sys 1.024 19.2 v v sysmin_ reg_acc minimum system voltage regulation accuracy (vbat below reg0x 3e() setting) reg0x 3e() = 0x3000h 12.288 v ? 2% 2% reg0x 3e() = 0x2400h 9.216 v ? 2% 2% reg0x 3e() = 0x1800h 6.144 v ? 3% 3% reg0x 3e() = 0x0e00h 3.584 v ? 3% 3% charge voltage regulation v bat_rn g battery voltage regulation 1.024 19.2 v
10 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics (continued) over t j = -40 c to 125 c (unless otherwise noted) parameter test conditions min typ max unit v bat_reg _acc battery voltage regulation accuracy (charge enable) (0 c to 85 c) reg0x 15() = 0x41a0h 16.8 v ? 0.5% 0.5% reg0x 15() = 0x3138h 12.6 v ? 0.5% 0.5% reg0x 15() = 0x20d0h 8.4 v ? 0.6% 0.6% reg0x 15() = 0x1068h 4.2 v ? 1.1% 1.2% charge current regulation in fast charge v ireg_ch g_rng charge current regulation differential voltage range v ireg_chg = v srp ? vsrn 0 81.28 mv i chrg_re g_acc charge current regulation accuracy 10- m sensing resistor, vbat above reg0x 3e() setting (0 c to 85 c) reg0x 14() = 0x1000h 4096 ma ? 3% 2% reg0x 14() = 0x0800h 2048 ma ? 4% 3% reg0x 14() = 0x0400h 1024 ma ? 5% 6% reg0x 14() = 0x0200h 512 ma ? 12% 12% charge current regulation in ldo mode i clamp pre-charge current clamp cell 2s-4s 384 ma cell 1 s, vsrn < 3 v 384 ma cell 1 s, 3 v < vsrn < vsysmin 2 a i prechrg _reg_acc pre-charge current regulation accuracy with 10-m srp/srn series resistor, vbat below reg0x 3e() setting (0 c to 85 c) reg0x 14() = 0x0180h 384 ma 2s-4s ? 15% 15% 1s ? 25% 25% reg0x 14() = 0x0100h 256 ma 2s-4s ? 20% 20% 1s ? 35% 35% reg0x 14() = 0x00c0h 192 ma 2s-4s ? 25% 25% 1s ? 50% 50% reg0x 14() = 0x0080h 128 ma 2s-4s ? 30% 30% i leak_srp _srn srp, srn leakage current mismatch (0 c to 85 c) ? 12 10 input current regulation v ireg_dp m_rng input current regulation differential voltage range v ireg_dpm = v acp ? v acn 0.5 64 mv i dpm_reg _acc input current regulation accuracy (-40 c to 105 c) with 10-m acp/acn series resistor reg0x 3f() = 0x4fffh 3800 4000 ma reg0x 3f() = 0x3bffh 2800 3000 ma reg0x 3f() = 0x1dffh 1300 1500 ma reg0x 3f() = 0x09ffh 300 500 ma i leak_acp _acn acp, acn leakage current mismatch (- 40 c to 105 c) ? 16 10 v ireg_dp m_rng_ili m voltage range for input current regulation (ilim_hiz pin) 1 4 v
11 BQ25710 www.ti.com slusd20 ? july 2018 product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics (continued) over t j = -40 c to 125 c (unless otherwise noted) parameter test conditions min typ max unit i dpm_reg _acc_ilim input current regulation accuracy on ilim_hiz pin v ilim_hiz = 1 v + 40 i dpm r ac , with 10-m acp/acn series resistor v ilim_hiz = 2.6 v 3800 4000 4200 ma v ilim_hiz = 2.2 v 2800 3000 3200 ma v ilim_hiz = 1.6 v 1300 1500 1700 ma v ilim_hiz = 1.2 v 300 500 700 ma i leak_ilim ilim_hiz pin leakage current ? 1 1 input voltage regulation v ireg_dp m_rng input voltage regulation range voltage on vbus 3.2 19.52 v v dpm_re g_acc input voltage regulation accuracy reg0x 3d()=0x3c80h 18688 mv ? 3% 2% reg0x 3d()=0x1e00h 10880 mv ? 4% 2.5% reg0x 3d()=0x0500h 4480 mv ? 5% 5% otg current regulation v iotg_re g_rng otg output current regulation differential voltage range v iotg_reg = v acp ? v ac n 0 81.28 mv i otg_acc otg output current regulation accuracy with 50-ma lsb and 10-m acp/acn series resistor reg0x 3c() = 0x3c00h 2800 3000 3200 ma reg0x 3c() = 0x1e00h 1300 1500 1700 ma reg0x 3c() = 0x0a00h 300 500 700 ma otg voltage regulation v otg_re g_rng otg voltage regulation range voltage on vbus 3 20.8 v v otg_re g_acc otg voltage regulation accuracy reg0x 3b() = 0x23f8h reg0x 32[2] = 0 20.002 v ? 2% 2% reg0x 3b() = 0x1710h reg0x 32[2] = 1 12.004 v ? 2% 2% reg0x 3b() = 0x099ch reg0x 32[2] = 1 5.002 v ? 3% 3% reference and buffer regn regulator v regn_r eg regn regulator voltage (0 ma ? 60 ma) v vbus = 10 v 5.7 6 6.3 v v dropou t regn voltage in drop out mode v vbus = 5 v, i load = 20 ma 3.8 4.3 4.6 v i regn_lim _charging regn current limit when converter is enabled v vbus = 10 v, force v regn =4 v 50 65 ma c regn regn output capacitor required for stability i load = 100 a to 50 ma 2.2 mf c vdda regn output capacitor required for stability i load = 100 a to 50 ma 1 mf quiescent current
12 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics (continued) over t j = -40 c to 125 c (unless otherwise noted) parameter test conditions min typ max unit i bat_batf et_on system powered by battery. batfet on. i srn + i srp + i sw2 + i btst2 + i sw1 + i btst1 + i acp + i acn + i vbus + i vsys vbat = 18 v, reg0x 12[15] = 1, in low power mode 22 45 a vbat = 18 v, reg0x 12[15] = 1, reg0x 30[13] = 1, regn off 125 195 a vbat = 18 v, reg0x 12[15] = 0, reg0x 30[12] = 0, regn on, dis_psys 880 1170 a vbat = 18 v, reg0x 12[15] = 0, reg0x 30[12] = 1, regn on, en_psys 980 1270 a i ac_sw_li ght_buck input current during pfm in buck mode, no load, i vbus + i acp + i acn + i vsys + i srp + i srn + i sw1 + i btst + i sw2 + i btst2 vin = 20 v, vbat = 12.6 v, 3s, reg0x 12[10] = 0; mosfet qg = 4 nc 2.2 ma i ac_sw_li ght_boost input current during pfm in boost mode, no load, i vbus + i acp + i acn + i vsys + i srp + i srn + i sw1 + i btst2 + i sw2 + i btst2 vin = 5 v, vbat = 8.4 v, 2s, reg0x 12[10] = 0; mosfet qg = 4 nc 2.7 ma i ac_sw_li ght_buckb oost input current during pfm in buck boost mode, no load, i vbus + i acp + i acn + i vsys + i srp + i srn + i sw1 + i btst1 + i sw2 + i btst2 vin = 12 v, vbat = 12 v, reg0x 12[10] = 0; mosfet qg = 4 nc 2.4 ma i otg_sta ndby quiescent current during pfm in otg mode i vbus + i acp + i acn + i vsys + i srp + i srn + i sw1 + i btst2 + i sw2 + i btst2 vbat = 8.4 v, vbus = 5 v, 800 khz switching frequency, mosfet qg = 4nc 3 ma vbat = 8.4 v, vbus = 12 v, 800 khz switching frequency, mosfet qg = 4nc 4.2 ma vbat = 8.4 v, vbus = 20 v, 800 khz switching frequency, mosfet qg = 4nc 6.2 ma v acp/n_o p input common mode range voltage on acp/acn 3.8 26 v v iadpt_c lamp i adpt output clamp voltage 3.1 3.2 3.3 v i iadpt i adpt output current 1 ma a iadpt input current sensing gain v (iadpt) / v (acp-acn) , reg0x 12[4] = 0 20 v/v v (iadpt) / v (acp-acn) , reg0x 12[4] = 1 40 v/v v iadpt_a cc input current monitor accuracy v (acp-acn) = 40.96 mv ? 2% 2% v (acp-acn) = 20.48 mv ? 3% 3% v (acp-acn) =10.24 mv ? 6% 6% v (acp-acn) = 5.12 mv ? 10% 10% c iadpt_m ax maximum capacitance at iadpt pin 100 pf v srp/n_o p battery common mode range voltage on srp/srn 2.5 18 v v ibat_cl amp ibat output clamp voltage 3.05 3.2 3.3 v i ibat ibat output current 1 ma a ibat charge and discharge current sensing gain on ibat pin v (ibat) / v (srn-srp) , reg0x 12[3] = 0, 8 v/v v (ibat) / v (srn-srp) , reg0x 12[3] = 1, 16 v/v i ibat_chg _acc charge and discharge current monitor accuracy on ibat pin v (srn-srp) = 40.96 mv ? 2% 2% v (srn-srp) = 20.48 mv ? 4% 4% v (srn-srp) =10.24 mv ? 7% 7% v (srn-srp) = 5.12 mv ? 15% 15% c ibat_ma x maximum capacitance at ibat pin 100 pf system power sense amplifier v psys psys output voltage range 0 3.3 v
13 BQ25710 www.ti.com slusd20 ? july 2018 product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics (continued) over t j = -40 c to 125 c (unless otherwise noted) parameter test conditions min typ max unit i psys psys output current 0 160 a psys psys system gain v (psys) / (p (in) +p (bat) ), reg0x 30[9] = 1 1 ma/w v psys_ac c psys gain accuracy (reg0x 30[9] = 1) adapter only with system power = 19.5 v / 45 w, ta = -40 c to 85 c ? 4% 4% battery only with system power = 11 v / 44 w, ta = ? 40 c to 85 c ? 3% 3% v psys_cl amp psys clamp voltage 3 3.3 v comparator vbus under voltage lockout comparator v vbus_uv loz vbus undervoltage rising threshold vbus rising 2.30 2.55 2.80 v v vbus_uv lo vbus undervoltage falling threshold vbus falling 2.18 2.40 2.62 v v vbus_uv lo_hyst vbus undervoltage hysteresis 150 mv v vbus_c onven vbus converter enable rising threshold vbus rising 3.2 3.5 3.9 v v vbus_c onvenz vbus converter enable falling threshold vbus falling 2.9 3.2 3.5 v v vbus_c onven_hy st vbus converter enable hysteresis 400 mv battery under voltage lockout comparator v vbat_uv loz vbat undervoltage rising threshold vsrn rising 2.35 2.55 2.75 v v vbat_uv lo vbat undervoltage falling threshold vsrn falling 2.2 2.4 2.6 v v vbat_uv lo_hyst vbat undervoltage hysteresis 150 mv v vbat_ot gen vbat otg enable rising threshold vsrn rising 3.25 3.55 3.85 v v vbat_ot genz vbat otg enable falling threshold vsrn falling 2.2 2.4 2.6 v v vbat_ot gen_hyst vbat otg enable hysteresis 1100 mv vbus under voltage comparator (otg mode) v vbus_ot g_uv vbus undervoltage falling threshold as percentage of reg0x 3b() 0.85 t vbus_ot g_uv vbus time undervoltage deglitch 7 ms vbus over voltage comparator (otg mode) v vbus_ot g_ov vbus overvoltage rising threshold as percentage of reg0x 3b() 1.1 t vbus_ot g_ov vbus time over-voltage deglitch 10 ms pre-charge to fast charge transition v bat_sys min_rise ldo mode to fast charge mode threshold, vsrn rising as percentage of 0x 3e() 0.98 1 1.02 v bat_sys min_fall ldo mode to fast charge mode threshold, vsrn falling as percentage of 0x 3e() 0.975 v bat_sys min_hyst fast charge mode to ldo mode threshold hysteresis as percentage of 0x 3e() 0.025
14 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics (continued) over t j = -40 c to 125 c (unless otherwise noted) parameter test conditions min typ max unit battery lowv comparator (pre-charge to fast charge threshold for 1s) v batlv_f all batlowv falling threshold 1 s 2.8 v v batlv_r ise batlowv rising threshold 3 v v batlv_r hyst batlowv hysteresis 200 mv input over-voltage comparator (acovp) v acov_ri se vbus overvoltage rising threshold vbus rising 25 26 27 v v acov_fa ll vbus overvoltage falling threshold vbus falling 23.5 24.5 25 v v acov_h yst vbus overvoltage hysteresis 1.5 v t acov_ris e_deg vbus deglitch overvoltage rising vbus converter rising to stop converter 100 ms t acov_fa ll_deg vbus deglitch overvoltage falling vbus converter falling to start converter 1 ms input over current comparator (acoc) v acoc acp to acn rising threshold, w.r.t. ilim2 in reg0x 33[15:11] voltage across input sense resistor rising, reg0x 31[2] = 1 1.8 2 2.2 v acoc_fl oor measure between acp and acn set idpm to minimum 44 50 56 mv v acoc_c eiling measure between acp and acn set idpm to maximum 172 180 188 mv t acoc_de g_rise rising deglitch time deglitch time to trigger acoc 250 ms t acoc_re lax relax time relax time before converter starts again 250 ms system over-voltage comparator (sysovp) v sysovp_ rise system overvoltage rising threshold to turn off converter 1 s 4.85 5 5.1 v 2 s 11.7 12 12.2 v 3 s, 4 s 19 19.5 20 v v sysovp_ fall system overvoltage falling threshold 1 s 4.8 v 2 s 11.5 v 3 s, 4 s 19 v i sysovp discharge current when sysovp stop switching was triggered on sys 20 ma bat over-voltage comparator (batovp) v batovp_ rise overvoltage rising threshold as percentage of vbat_reg in reg0x 15() 1 s, 4.2 v 1.025 1.04 1.06 2 s - 4 s 1.025 1.04 1.05 v batovp_ fall overvoltage falling threshold as percentage of vbat_reg in reg0x 15() 1 s 1 1.02 1.04 2 s - 4 s 1 1.02 1.03 v batovp_ hyst overvoltage hysteresis as percentage of vbat_reg in reg0x 15() 1 s 0.02 2 s - 4 s 0.02 i batovp discharge current during batovp on vsys pin 20 ma t batovp_ rise overvoltage rising deglitch to turn off batdrv to disable charge 20 ms converter over-current comparator (q2)
15 BQ25710 www.ti.com slusd20 ? july 2018 product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics (continued) over t j = -40 c to 125 c (unless otherwise noted) parameter test conditions min typ max unit vocp_li mit_q2 converter over-current limit reg0x 31[5]=1 150 mv reg0x 31[5]=0 210 mv vocp_li mit_sys short_ q2 system short or srn < 2.4 v reg0x 31[5]=1 45 mv reg0x 31[5]=0 60 mv converter over-current comparator (acx) vocp_li mit_acx converter over-current limit reg0x 31[4]=1 150 mv reg0x 31[4]=0 280 mv vocp_li mit_sys short_ acx system short or srn < 2.4 v reg0x 31[4]=1 90 mv reg0x 31[4]=0 150 mv thermal shutdown comparator t shut_ri se thermal shutdown rising temperature temperature increasing 155 c t shutf_f all thermal shutdown falling temperature temperature reducing 135 c t shut_hy s thermal shutdown hysteresis 20 c t shut_rd eg thermal deglitch shutdown rising 100 ms t shut_fh ys thermal deglitch shutdown falling 12 ms vsys prochot comparator vsys_t h1 vsys_th1 comparator falling threshold reg0x 33[7:4] = 0111, 2-4 s 6.6 v reg0x 33[7:4] = 0100, 1 s 3.5 v vsys_t h2 vsys_th2 comparator falling threshold reg0x 33[3:2] = 10, 2-4 s 6.5 v reg0x 33[3:2] = 10, 1 s 3.5 v t sys_pro _falling_de g v sys falling deglitch for throttling 4 s icrit prochot comparator v icrit_pr o input current rising threshold for throttling as 10% above ilim2 (reg0x 33[15:11]) only when ilim2 setting is higher than 2a 1.05 1.1 1.17 inom prochot comparator v inom_pr o inom rising threshold as 10% above iin (reg0x 3f()) 1.05 1.1 1.16 idchg prochot comparator v idchg_p ro idchg threshold for throttling for idschg of 6 a reg0x 34[15:10] = 001100 6272 ma 0.95 1.03 independent comparator v indep_c mp independent comparator threshold reg0x 30[7] = 1, cmpin falling 1.17 1.2 1.23 v reg0x 30[7] = 0, cmpin falling 2.27 2.3 2.33 v v indep_c mp_hys independent comparator hysteresis reg0x 30[7] = 0, cmpin falling 100 mv power mosfet driver pwm oscillator and ramp f sw pwm switching frequency reg0x 12[9] = 0 1020 1200 1380 khz reg0x 12[9] = 1 680 800 920 khz batfet gate driver (batdrv)
16 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics (continued) over t j = -40 c to 125 c (unless otherwise noted) parameter test conditions min typ max unit v batdrv_ on gate drive voltage on batfet 8.5 10 11.5 v v batdrv_ diode drain-source voltage on batfet during ideal diode operation 30 mv r batdrv_ on measured by sourcing 10 a current to batdrv 2.5 4 6 k r batdrv_ off measured by sinking 10 a current from batdrv 1.2 2.1 k pwm high side driver (hidrv q1) r ds_hi_o n_q1 high side driver (hsd) turn on resistance v btst1 - v sw1 = 5 v 6 r ds_hi_o ff_q1 high side driver turn off resistance v btst1 - v sw1 = 5 v 1.3 2.2 v btst1_r efresh bootstrap refresh comparator falling threshold voltage v btst1 - v sw1 when low side refresh pulse is requested 3.2 3.7 4.6 v pwm high side driver (hidrv q4) r ds_hi_o n_q4 high side driver (hsd) turn on resistance v btst2 - v sw2 = 5 v 6 r ds_hi_o ff_q4 high side driver turn off resistance v btst2 - v sw2 = 5 v 1.5 2.4 v btst2_r efresh bootstrap refresh comparator falling threshold voltage v btst2 - v sw2 when low side refresh pulse is requested 3.1 3.7 4.5 v pwm low side driver (lodrv q2) r ds_lo_o n_q2 low side driver (lsd) turn on resistance v btst1 - v sw1 = 5.5 v 6 r ds_lo_o ff_q2 low side driver turn off resistance v btst1 - v sw1 = 5.5 v 1.7 2.6 pwm low side driver (lodrv q3) r ds_lo_o n_q3 low side driver (lsd) turn on resistance v btst2 - v sw2 = 5.5 v 7.6 r ds_lo_o ff_q3 low side driver turn off resistance v btst2 - v sw2 = 5.5 v 2.9 4.6 internal soft start during charge enable ssstep _dac soft start step size 64 ma ssstep _dac soft start step time 8 ms integrated btst diode (d1) v f_d1 forward bias voltage if = 20 ma at 25 c 0.8 v v r_d1 reverse breakdown voltage ir = 2 a at 25 c 20 v integrated btst diode (d2) v f_d2 forward bias voltage if = 20 ma at 25 c 0.8 v v r_d2 reverse breakdown voltage ir = 2 a at 25 c 20 v interface logic input (sda, scl, en_otg) v in_ lo input low threshold smbus 0.8 v v in_ hi input high threshold smbus 2.1 v logic output open drain (sda, chrg_ok, cmpout) v out_ lo output saturation voltage 5 ma drain current 0.4 v v out_ leak leakage current v = 7 v ? 1 1 ma
17 BQ25710 www.ti.com slusd20 ? july 2018 product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics (continued) over t j = -40 c to 125 c (unless otherwise noted) parameter test conditions min typ max unit logic output open drain sda v out_ lo_sda output saturation voltage 5 ma drain current 0.4 v v out_ leak_sda leakage current v = 7v ? 1 1 ma logic output open drain chrg_ok v out_ lo_chrg_ ok output saturation voltage 5 ma drain current 0.4 v v out_ leak _chrg_ok leakage current v = 7v ? 1 1 ma logic output open drain cmpout v out_ lo_cmpo ut output saturation voltage 5 ma drain current 0.4 v v out_ leak _cmpout leakage current v = 7v ? 1 1 ma logic output open drain (prochot) v out_ lo_proch ot output saturation voltage 50 pullup to 1.05 v / 5-ma 300 mv v out_ leak_pro chot leakage current v = 5.5 v ? 1 1 ma analog input (ilim_hiz) v hiz_ lo voltage to get out of hiz mode ilim_hiz pin rising 0.8 v v hiz_ high voltage to enable hiz mode ilim_hiz pin falling 0.4 v analog input (cell_batpresz) v cell_4s 4s regn of regn = 6 v, as percentage 0.684 0.75 v cell_3s 3s regn of regn = 6 v, as percentage 0.517 0.55 0.65 v cell_2s 2s regn of regn = 6 v, as percentage 0.35 0.4 0.491 v cell_1s 1s regn of regn = 6 v, as percentage 0.184 0.25 0.316 v cell_ba tpresz_ri se battery is present cell_batpresz rising 0.18 v cell_ba tpresz_f all battery is removed cell_batpresz falling 0.15 8.6 timing requirements min nom max unit smbus timing characteristics t r sclk/sdata rise time 1 s t f sclk/sdata fall time 300 ns t w(h) sclk pulse width high 4 50 s t w(l) sclk pulse width low 4.7 s t su(sta) setup time for start condition 4.7 s t h(sta) start condition hold time after which first clock pulse is generated 4 s t su(dat) data setup time 250 ns
18 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated timing requirements (continued) min nom max unit (1) devices participating in a transfer will timeout when any clock low exceeds the 25ms minimum timeout period. devices that have detected a timeout condition must reset the communication no later than the 35 ms maximum timeout period. both a master and a slave must adhere to the maximum value specified as it incorporates the cumulative stretch limit for both a master (10 ms) and a slave (25 ms). (2) user can adjust threshold via smbus chargeoption() reg0x 12(). t h(dat) data hold time 300 ns t su(stop) setup time for stop condition 4 s t (buf) bus free time between start and stop condition 4.7 s f s(cl) clock frequency 10 100 khz host communication failure t timeout smbus bus release timeout (1) 25 35 ms t deg_wd deglitch for watchdog reset signal 10 ms t wdi watchdog timeout period, chargeoption() bit [14:13] = 01 (2) 4 5.5 7 s watchdog timeout period, chargeoption() bit bit [14:13] = 10 (2) 70 88 105 s watchdog timeout period, chargeoption() bit bit [14:13] = 11 (2) 140 175 210 s 8.7 typical characteristics vin = 5 v figure 1. light load efficiency vin = 12 v figure 2. light load efficiency vin = 20 v figure 3. light load efficiency vin = 5 v figure 4. system efficiency output current (a) efficiency (%) 0 0.01 0.02 0.03 0.04 0.05 60 65 70 75 80 85 90 d001 vout = 6.1 v vout = 8.4 v vout = 9.2 v vout = 12.5 v output current (a) efficiency (%) 0 0.01 0.02 0.03 0.04 0.05 60 65 70 75 80 85 90 d001 vout = 6.1 v vout = 8.4 v vout = 9.2 v vout = 12.5 v output current (a) efficiency (%) 0 0.01 0.02 0.03 0.04 0.05 60 65 70 75 80 85 90 d001 vout = 6.1 v vout = 8.4 v vout = 9.2 v vout = 12.5 v output current (a) efficiency (%) 0 1 2 3 4 5 6 80 82 84 86 88 90 92 94 96 d001 vout = 3.7 v vout = 7.4 v vout = 11.1 v vout = 14.8 v
19 BQ25710 www.ti.com slusd20 ? july 2018 product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) vin = 9 v figure 5. system efficiency vin = 12 v figure 6. system efficiency vin = 20 v figure 7. system efficiency figure 8. otg efficiency with 1s battery figure 9. otg efficiency with 2s battery figure 10. otg efficiency with 3s battery output current (a) efficiency (%) 0 1 2 3 4 5 80 82 84 86 88 90 92 94 96 d001 votg = 5 v votg = 12 v votg = 20 v output current (a) efficiency (%) 0 1 2 3 4 5 6 80 82 84 86 88 90 92 94 96 98 d001 vout = 3.7 v vout = 7.4 v vout = 11.1 v vout = 14.8 v output current (a) efficiency (%) 0 1 2 3 4 5 6 80 82 84 86 88 90 92 94 96 98 d001 votg = 5 v votg = 12 v votg = 20 v output current (a) efficiency (%) 0 1 2 3 4 5 6 80 82 84 86 88 90 92 94 96 98 d001 vout = 3.7 v vout = 7.4 v vout = 11.1 v vout = 14.8 v output current (a) efficiency (%) 0 1 2 3 4 5 6 80 82 84 86 88 90 92 94 96 d001 votg = 5 v votg = 12 v votg = 20 v output current (a) efficiency (%) 0 1 2 3 4 5 6 80 82 84 86 88 90 92 94 96 98 d001 vout = 3.7 v vout = 7.4 v vout = 11.1 v vout = 14.8 v
20 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) figure 11. otg efficiency with 4s battery output current (a) efficiency (%) 0 1 2 3 4 5 6 80 82 84 86 88 90 92 94 96 98 d001 votg = 5 v votg = 12 v votg = 20 v
21 BQ25710 www.ti.com slusd20 ? july 2018 product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated 9 detailed description 9.1 overview the BQ25710 is a narrow vdc buck-boost charger controller for portable electronics such as notebook, detachable, ultrabook, tablet and other mobile devices with rechargeable batteries. it provides seamless transition among different converter operation modes (buck, boost, or buck boost), fast transient response, and high light load efficiency. BQ25710 supports wide range of power sources, including usb pd ports, legacy usb ports, traditional acdc adapters, etc. it takes input voltage from 3.5 v to 24 v, and charges battery of 1-4 series. in the absence of an input source, BQ25710 supports usb on-the-go (otg) function from 1-4 cell battery to generate adjustable 3 v ~ 20.8 v at usb port with 8mv resolution. the otg output voltage transition slew rate can be configurable, which complies with the usb power delivery 3.0 pps specifications. when only the battery powers the system and no external load is connected to the usb otg port, BQ25710 provides the vmin active protection (vap) feature. in the vap operation, BQ25710 first charges up the voltage of the input decoupling capacitors at vbus to store a certain amount of energy. during the system peak power spike, the huge current drawn from the battery introduces a larger voltage drop across the impedance from the battery to the system. then the energy stored in the input capacitors will supplement the system, to prevent the system voltage from drooping below the minimum system voltage and leading the system to black screen. this vap is designed to absorb system power peaks during the periods of high demand to improve the system turbo performance, which is highly recommended by intel for the platforms with 1s~2s battery. BQ25710 features dynamic power management (dpm) to limit the input power and avoid ac adapter overloading. during battery charging, as the system power increases, the charging current will reduce to maintain total input current below adapter rating. if system power demand temporarily exceeds adapter rating, BQ25710 supports nvdc architecture to allow battery discharge energy to supplement system power. for details, refer to system voltage regulation section. in order to be compliant with an intel imvp8 / imvp9 compliant system, BQ25710 includes psys function to monitor the total platform power from adapter and battery. besides psys, it provides both an independent input current buffer (iadpt) and a battery current buffer (ibat) with highly accurate current sense amplifiers. if the platform power exceeds the available power from adapter and battery, a prochot signal is asserted to cpu so that the cpu optimizes its performance to the power available to the system. the smbus controls input current, charge current and charge voltage registers with high resolution, high accuracy regulation limits. it also sets the prochot timing and threshold profile to meet system requirements.
22 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.2 functional block diagram 50ms rising deglitch 20x** 20x** regn ldo smbus interface chargeoption0() chargeoption1() chargeoption2() chargecurrent() chargevoltage() inputcurrent() inputvoltage() minsysvoltage() otgvoltage() otgcurrent() 3.9v acovp 26v chrg_ok_drv vref_idpm, or vref_iotg en_hiz pwm en_regn vbus chrg_ok acp acn iadpt srp srn sda scl pgnd lodrv1 regn sw1 hidrv1 btst1 vref_vbat BQ25710 block diagram ** programmable in register 4 2 3 pwm driver logic ibat psys cell_batpresz processor hot prochot iadpt ibat vsys acn (acp-acn) srn (srn-srp) 16x vref_ichg ilim_hiz lodrv2 sw2 hidrv2 btst2 cmpin cmpout vref_cmp** cmp_deg** loop selector and error amplifier vref_vdpm or vref_votg vref_ilim vsns_idpm, or vsns_iotg vsns_ichg vsns_vbat vsys vsns_vsys vref_vsys vsns_vdpm or vsys_votg over current over voltage detect vsns_vsys vsns_vbat vsns_ichg vsns_idchg vsns_idpm vsns_vdpm vsns_idchg loop regulation reference vref_vsys vref_vbat vref_ichg vref_idpm vref_vdpm en_learn en_ldo en_chrg en_hiz en_learn en_ldo en_chrg batdrv vsys vsys-10v ldo mode gate control batpresz chrg_ok decoder cell_config comp1 comp2 decoder en_hiz en_otg en_otg otg/vap vdda 8 9 10 vsns_ichg vref_iotg vref_votg 1 6 20 19 22 12 13 5 11 18 26 23 27 24 25 29 28 7 32 31 30 21 17 16 15 14 en_regn 50ms rising deglitch
23 BQ25710 www.ti.com slusd20 ? july 2018 product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.3 feature description 9.3.1 power-up from battery without dc source if only battery is present and the voltage is above v vbat_uvloz , the batfet turns on and connects battery to system. by default, the charger is in low power mode (reg 0x12[15] = 1) with lowest quiescent current. the ldo stays off. when device moves to performance mode (reg 0x12[15] = 0), the host can enable ibat buffer through smbus to monitor discharge current. the psys, prochot or independent comparator also can be enabled by the host through the smbus commands. in performance mode, the regn ldo is always available to provide an accurate reference for the other features. 9.3.2 vmin active protection (vap) when battery only mode in vap mode operation, the buck-boost charger delivers the energy from the battery to charge the voltage of the input decoupling capacitors (vbus) as high as possible (like 20v). the system peak power pulse for a 2s1p or 1s2p system can be as high as 100w if the soc and motherboard systems spikes coincide. these spikes are expected to be very rare, but possible. during these high power spikes, the charger is expected to supplement the battery (drawing the power from the charger ? s input decoupling capacitors) to prevent the system voltage from drooping. vap allows the soc to set much higher peak power levels to the sooc, thus provides for much better turbo performance. follows the steps below to enter vap operation.: 1. set the voltage limit to charge vbus in reg 0x3b(). 2. set the current limit to charge vbus in reg 0x3c() and reg 0x34[15:10]. 3. set the system voltage regulation point in reg 0x3e[13:8], when the input cap supplements battery, the vsys_min regulation loop will maintain vsys at this regulation point. 4. set the prochot_vsys_th1 threshold to trigger the vap discharging vbus in reg 0x33[7:4]. 5. set the prochot_vsys_th2 threshold to assert /prochot active low signal to throttle soc in reg 0x33[3:2]. 6. enable the vap mode by setting reg 0x32[5] = 0, reg 0x32[12] = 0, and pulling the otg/vap pin to high. to exit vap mode, the host should write either reg 0x32[5] = 1 or pull low the otg/vap to low. any regular fault conditions of the charger in vap mode will reset reg 0x32[5] = 1, and the charger will exit vap mode automatically. 9.3.3 power-up from dc source when an input source plugs in, the charger checks the input source voltage to turn on ldo and all the bias circuits. it sets the input current limit before the converter starts. the power-up sequence from dc source is as follows: 1. 50 ms after vbus above v vbus_conven , enable 6 v ldo and chrg_ok goes high 2. input voltage and current limit setup 3. battery cell configuration 4. 150 ms after vbus above v vbus_conven , converter powers up. 9.3.3.1 chrg_ok indicator chrg_ok is an active high open drain indicator. it indicates the charger is in normal operation when the following conditions are valid: ? vbus is above v vbus_conven ? vbus is below v acov ? no mosfet/inductor, or over-voltage, over-current, thermal shutdown fault 9.3.3.2 input voltage and current limit setup after chrg_ok goes high, the charger sets default input current limit in reg 0x3f() to 3.30 a. the actual input current limit being adopted by the device is the lower setting of reg 0x3f() and pin.
24 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) charger initiates a vbus voltage measurement without any load (vbus at no load) right before the converter is enabled. the default vindpm threshold is vbus at no load ? 1.28 v. after input current and voltage limits are set, the charger device is ready to power up. the host can always program the input current and voltage limit after the charger being powered up, based on the input source type. 9.3.3.3 battery cell configuration cell_batpresz pin is biased with a resistor divider from regn to cell_batpresz to gnd. after vdda ldo is activated, the device detects the battery configuration through cell_batpresz pin bias voltage. refer to table 1 for cell setting thresholds. table 1. battery cell configuration cell count pin voltage w.r.t. vdda battery voltage (reg0x 15) sysovp 4s 75% 16.800 v 19.5 v 3s 55% 12.592 v 19.5 v 2s 40% 8.400 v 12 v 1s 25% 4.192 v 5 v 9.3.3.4 device hi-z state the charger enters hi-z mode when ilim_hiz pin voltage is below 0.4 v or reg0x 32[15] is set to 1. during hi-z mode, the input source is present, and the charger is in the low quiescent current mode with regn ldo enabled. 9.3.4 usb on-the-go (otg) the device supports usb otg operation to deliver power from the battery to other portable devices through usb port. the otg mode output voltage is set in reg0x 3b(). the otg mode output current is set in reg0x 3c(). the otg operation can be enabled if the conditions are valid: ? valid battery voltage is set reg0x 15(), the battery voltage should not trip the batovp threshold, otherwise, the converter will stop switching. ? otg output voltage is set in reg0x 3b() and reg0x 32[2], if reg0x 32[2] = 0, the votg digital dac is offset by 1.28v to achieve higher range from 4.28v~20.8v, if reg0x 32[2] = 1, the votg digital dac is from 3v to 19.52v. ? otg output current is set in reg0x 3c(). ? en_otg pin is high, reg0x 32[12] = 1 and reg0x 32[5] = 1. ? vbus is below v vbus_uvlo . ? 10 ms after the above conditions are valid, converter starts and vbus ramps up to target voltage. chrg_ok pin goes high if reg0x12[11] = 1. 9.3.5 converter operation the charger employs a synchronous buck-boost converter that allows charging from a standard 5-v or a high- voltage power source. the charger operates in buck, buck-boost and boost mode. the buck-boost can operate uninterruptedly and continuously across the three operation modes. table 2. mosfet operation mode buck buck-boost boost q1 switching switching on q2 switching switching off q3 off switching switching q4 on switching switching
25 BQ25710 www.ti.com slusd20 ? july 2018 product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.3.5.1 inductance detection through iadpt pin the charger reads the inductance value through the resistance tied to iadpt pin before the converter starts up. the resistances recommended for 1uh, 2.2uh and 3.3uh inductance are 93k , 137k and 169k , respectively. a surface mount chip resistor with 3% or better tolerance must to be used for an accurate inductance detection. table 3. inductor detection through iadpt resistance inductor in use resistor on iadpt pin 1 h 93 k 2.2 h 137 k 3.3 h 169 k 9.3.5.2 continuous conduction mode (ccm) with sufficient charge or system current, the inductor current does not cross 0 a, which is defined as ccm. the controller starts a new cycle with ramp coming up from 200 mv. as long as the error amplifier output voltage is above the ramp voltage, the high-side mosfet (hsfet) stays on. when the ramp voltage exceeds error amplifier output voltage, hsfet turns off and low-side mosfet (lsfet) turns on. at the end of the cycle, ramp gets reset and lsfet turns off, ready for the next cycle. there is always break-before-make logic during transition to prevent cross-conduction and shoot-through. during the dead time when both mosfets are off, the body-diode of the low-side power mosfet conducts the inductor current. during ccm, the inductor current always flows and creates a fixed two-pole system. having the lsfet turn-on when the hsfet is off keeps the power dissipation low and allows safe charging at high currents. 9.3.5.3 pulse frequency modulation (pfm) in order to improve converter light-load efficiency, BQ25710 switches to pfm operation at light load. the effective switching frequency will decrease accordingly when system load decreases. the minimum frequency can be limit to 25 khz when the ooa feature is enabled (chargeoption0() bit[10]=1). 9.3.6 current and power monitor 9.3.6.1 high-accuracy current sense amplifier (iadpt and ibat) as an industry standard, a high-accuracy current sense amplifier (csa) is used to monitor the input current during forward charging, or output current during otg (iadpt) and the charge/discharge current (ibat). iadpt voltage is 20 or 40 the differential voltage across acp and acn. ibat voltage is 8x/16 (during charging), or 8 /16 (during discharging) of the differential across srp and srn. after input voltage or battery voltage is above uvlo, iadpt output becomes valid. to lower the voltage on current monitoring, a resistor divider from csa output to gnd can be used and accuracy over temperature can still be achieved. ? v (iadpt) = 20 or 40 (v (acp) ? v (acn) ) during forward mode, or 20 or 40 (v (acn) ? v (acp) ) during reverse otg mode. ? v (ibat) = 8 or 16 (v (srp) ? v (srn) ) during forward mode. ? v (ibat) = 8 or 16 (v (srn) ? v (srp) ) during forward supplement mode, or reverse otg mode. a maximum 100-pf capacitor is recommended to connect on the output for decoupling high-frequency noise. an additional rc filter is optional, if additional filtering is desired. note that adding filtering also adds additional response delay. the csa output voltage is clamped at 3.3 v. 9.3.6.2 high-accuracy power sense amplifier (psys) the charger monitors total system power. during forward mode, the input adapter powers system. during reverse otg mode, the battery powers the system and vbus output. the ratio of psys pin output current and total system power, k psys , can be programmed in reg0x 30[9] with default 1 a/w. the input and charge sense resistors (rac and rsr) are selected in reg0x 30[11:10]. psys voltage can be calculated with equation 1 , where i in > 0 i bat < 0 when the charger is in forward charging with an adapter connected, and i bat > 0 when the battery is in discharging mode. (1) for proper psys functionality, rac and rsr values are limited to 10 m and 20 m . psys psys psys acp in bat bat v r k (v i v i ) u u u
26 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated to minimize the quiescent current, the psys function is disabled by default. it can be enabled by setting reg0x 30[12] = 1. 9.3.7 input source dynamic power manage refer to input current and input voltage registers for dynamic power management . 9.3.8 two-level adapter current limit (peak power mode) usually adapter can supply current higher than dc rating for a few milliseconds to tens of milliseconds. the charger employs two-level input current limit, or peak power mode, to fully utilize the overloading capability and minimize battery discharge during cpu turbo mode. peak power mode is enabled in reg0x 31[13:12]. the dc current limit, or i lim1 , is the same as adapter dc current, set in reg 0x3f(). the overloading current, or i lim2 , is set in reg0x 33[15:11], as a percentage of i lim1. when the charger detects input current surge and battery discharge due to load transient (both the adaper and battery support the system together), or when the charger detects the system voltage starts to drop due to load transient (only the adaper supports the system), the charger will first apply i lim2 for t ovld in reg0x 31[15:14], and then i lim1 for up to t max ? t ovld time. t max is programmed in reg0x 31[9:8]. after t max, if the load is still high, another peak power cycle starts. charging is disabled during t max, ; once t max, expires, charging continues. if t ovld is programmed to be equal to t max , then peak power mode is always on. figure 12. two-level adapter current limit timing diagram 9.3.9 processor hot indication when cpu is running turbo mode, the system peak power may exceed available power from adapter and battery together. the adapter current and battery discharge peak current, or system voltage drop is an indication that system power is too high. the charger processor hot function monitors these events, and prochot pulse is asserted if the system power is too high. once cpu receives prochot pulse from charger, it slows down to reduce system power. the events monitored by the processor hot function includes: ? icrit: adapter peak current, as 110% of i lim2 ? inom: adapter average current (110% of input current limit) ? idchg: battery discharge current ? vsys: system voltage on vsys ? adapter removal: upon adapter removal (chrg_ok pin high to low) ? battery removal: upon battery removal (cell_batpresz pin goes low) ? cmpout: independent comparator output (cmpout pin high to low) t ovld t max t ovld ivbus prochot i lim1 i lim2 i crit isys ibat battery discharge
27 BQ25710 www.ti.com slusd20 ? july 2018 product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated ? vdpm: vbus lower than 80%/90%/100% of vindpm threshold. ? exit_vap: every time when the charger exits vap mode. the threshold of icrit, idchg, vsys or vdpm, and the deglitch time of icrit, inom, idchg or cmpout are programmable through smbus. except the prochot_exit_vap is always enabled, the other triggering events can be individually enabled in reg0x 34[7:0]. when any enabled event in prochot profile is triggered, prochot is asserted low for a single pulse with minimal width programmable in reg0x 21[13:12]. at the end of the single pulse, if the prochot event is still active, the pulse gets extended until the event is removed. if the prochot pulse extension mode is enabled by setting reg0x 21[14] = 1, the prochot pin will be kept as low until host writes reg0x 21[11]21[11] = 0, even if the triggering event has been removed. if the prochot_vdpm or prochot_exit_vap is triggered, prochot pin will always stay low until the host clears it, no matter the prochot is in one pulse mod or in extended mode. figure 13. prochot profile 10ms debounce prochot ? 10ms + pp_icrit vdd icrit iadpt + pp_inom inom low pass filter + pp_idchg idchg_vth idchg + pp_vsys vsys_vth v_srp + pp_vdpm a*vdpm vbus exit_vap (triggered by in_vap falling edge) pp_cmp pp_batpres pp_acok cell_batpresz (one shot on pin falling edge) cmpout chrg_ok (one shot on pin falling edge) < 0.3v adjustable deglitch fixed deglitch
28 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.3.9.1 prochot during low power mode during low power mode (reg0x 12[15] = 1), the charger offers a low power prochot function with very low quiescent current consumption (~150ua), which uses the independent comparator to monitor the system voltage, and assert prochot to cpu if the system power is too high. below lists the register setting to enable prochot monitoring system voltage in low power mode. ? reg 0x12[15] = 1 to enable charger low power mode. ? reg0x 34[7:0] = 00h ? reg0x30[6:4] = 100 ? independent comparator threshold is always 1.2 v ? when reg0x 30[13] = 1, charger monitors system voltage. connect cmpin to voltage proportional to system. prochot triggers from high to low when cmpin voltage rises above 1.2 v. figure 14. prochot low power mode implementation 9.3.9.2 prochot status reg0x21[8:0] reports which event in the profile triggers prochot if the corresponding bit is set to 1. the status bit can be reset back to 0 after it is read by host, when the current prochot event is not active any more. assume there are two prochot events, event a and event b. event a triggers prochot first, but event b is also active. both status bits will be high. at the end of the 10 ms prochot pulse, if any of the prochot event is still active (either a or b), the prochot pulse is extended. 9.3.10 device protection 9.3.10.1 watchdog timer the charger includes watchdog timer to terminate charging if the charger does not receive a write maxchargevoltage() or write chargecurrent() command within 175 s (adjustable via reg0x 12[14:13]). when watchdog timeout occurs, all register values are kept unchanged except chargecurrent() resets to zero. battery charging is suspended. write maxchargevoltage() or write chargecurrent() commands must be re-sent to reset watchdog timer and resume charging. writing reg0x 12[14:13] = 00 to disable watchdog timer also resumes charging. prochot independent comparator 1.2 v BQ25710 cmpin v sys v voltage
29 BQ25710 www.ti.com slusd20 ? july 2018 product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.3.10.2 input overvoltage protection (acov) the charger has fixed acov voltage. when vbus pin voltage is higher than acov, it is considered as adapter over voltage. chrg_ok will be pulled low, and converter will be disabled. as system falls below battery voltage, batfet will be turned on. when vbus pin voltage falls below acov, it is considered as adapter voltage returns back to normal voltage. chrg_ok is pulled high by external pull up resistor. the converter resumes if enable conditions are valid. 9.3.10.3 input overcurrent protection (acoc) if the input current exceeds the 1.33 or 2 (reg0x 31[2]) of i lim2_vth (reg0x 33[15:11]) set point, converter stops switching. after 300 ms, converter starts switching again. 9.3.10.4 system overvoltage protection (sysovp) when the converter starts up, BQ25710 reads cell pin configuration and sets maxchargevoltage() and sysovp threshold (1s ? 5 v, 2s ? 12 v, 3s/4s ? 19.5 v). before regx 15() is written by the host, the battery configuration will change with cell pin voltage. when sysovp happens, the device latches off the converter. reg0x20[4] is set to 1. the user can clear latch-off by either writing 0 to the sysovp bit or removing and plugging in the adapter again. after latch-off is cleared, the converter starts again. 9.3.10.5 battery overvoltage protection (batovp) battery over-voltage may happen when battery is removed during charging or the user plugs in a wrong battery. the batovp threshold is 104% (1 s) or 102% (2 s to 4 s) of regulation voltage set in reg0x 15(). 9.3.10.6 battery short if bat voltage falls below sysmin during charging, the maximum current is limited to 384 ma. 9.3.10.7 system short hiccup mode vsys pin is monitoring the system voltage, when vsys is lower than 2.4v, after 2ms deglitch time, the charger will be shut down for 500ms. the charger will restart for 10ms and measure vsys again, if it is still lower than 2.4v, the charger will be shut down again. this hiccup mode will be tried continuously, if the charger restart is failed for 7 times in 90 second, the charger will be latched off. reg0x 20[3] will be set to 1 to report a system short fault. the charger only can be enabled again once the host writes reg0x 12[6] = 1. the charger system short hiccup mode can be disabled by writing 9.3.10.8 thermal shutdown (tshut) the wqfn package has low thermal impedance, which provides good thermal conduction from the silicon to the ambient, to keep junction temperatures low. as added level of protection, the charger converter turns off for self- protection whenever the junction temperature exceeds the 155 c. the charger stays off until the junction temperature falls below 135 c. during thermal shut down, the ldo current limit is reduced to 16 ma and regn ldo stays off. when the temperature falls below 135 c, charge can be resumed with soft start. 9.4 device functional modes 9.4.1 forward mode when input source is connected to vbus, BQ25710 is in forward mode to regulate system and charge battery. 9.4.1.1 system voltage regulation with narrow vdc architecture BQ25710 employs narrow vdc architecture (nvdc) with batfet separating system from battery. the minimum system voltage is set by minsystemvoltage(). even with a deeply depleted battery, the system is regulated above the minimum system voltage. when the battery is below minimum system voltage setting, the batfet operates in linear mode (ldo mode). as the battery voltage rises above the minimum system voltage, batfet is fully on when charging or in supplement mode and the voltage difference between the system and battery is the vds of batfet. system voltage is regulated 160 mv above battery voltage when batfet is off (no charging or no supplement current).
30 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated device functional modes (continued) the batdrv pin is only able to drive a battery mosfet with ciss lower than 5nf. the ciss in the range of 1nf~3nf is recommended. see system voltage regulation for details on system voltage regulation and register programming. 9.4.1.2 battery charging BQ25710 charges 1-4 cell battery in constant current (cc), and constant voltage (cv) mode. based on cell_batprez pin setting, the charger sets default battery voltage 4.2v/cell to chargevoltage(), or reg 0x15(). according to battery capacity, the host programs appropriate charge current to chargecurrent(), or reg 0x14(). when battery is full or battery is not in good condition to charge, host terminates charge by setting reg0x 12[0] to 1, or setting chargecurrent() to zero. see feature description for details on register programming. 9.4.2 usb on-the-go BQ25710 supports usb otg functionality to deliver power from the battery to other portable devices through usb port (reverse mode). the otg output voltage is compliant with usb pd specification, including 5 v, 9 v, 15 v, and 20 v. the output current regulation is compliant with usb type c specification, including 500 ma, 1.5 a, 3 a and 5 a. similar to forward operation, the device switches from pwm operation to pfm operation at light load to improve efficiency. 9.4.3 pass through mode (ptm) when the system is in the sleep mode or lgith load condition, the charger can be operated in the pass through mode to improve the light load efficiency. in ptm, the buck and boost high side fets are both turned on, while the buck and boost low side fets are both turned off. the input power is directly passed through the charger to the system. the switching losses of mosfets and the inductor core loss are saved. device will be transition from normal buck-boost operation to ptm operation by: ? set reg 0x31[7] = 0, to disable the en_exitilim. ? set reg 0x30[8] = 1. ? set reg 0x30[2] = 1. ? ground ilim_hiz pin. device will transition out of ptm mode with host control by: ? set reg 0x30[2] = 0. ? pull ilim_hiz pin to high. ? device exits ptm to buck-boost operation if tripping vindpm. ? device exits ptm to buck-boost operation under fault conditions (for examples acoc, tshut, batoc, batov). 9.5 programming the charger supports battery-charger commands that use either write-word or read-word protocols, as summarized in smbus write-word and read-word protocols section 8.5.1.1 . the smbus address is 12h. the manufacturerid and deviceid registers are assigned identify the charger device. the manufacturerid register command always returns 40h. 9.5.1 smbus interface the BQ25710 device operates as a slave, receiving control inputs from the embedded controller host through the smbus interface. the BQ25710 device uses a simplified subset of the commands documented in system management bus specification v1.1 , which can be downloaded from www.smbus.org . the BQ25710 device uses the smbus read-word and write-word protocols (shown in table 4 and table 5 ) to communicate with the smart battery. the device performs only as a smbus slave device with address 0b00010010 (0x12h) and does not initiate communication on the bus. in addition, the device has two identification registers, a 16-bit device id register (0xffh) and a 16-bit manufacturer id register (0xfeh).
31 BQ25710 www.ti.com slusd20 ? july 2018 product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated programming (continued) smbus communication starts when vcc is above v (uvlo) . the data (sda) and clock (scl) pins have schmitt-trigger inputs that can accommodate slow edges. choose pullup resistors (10 k ) for sda and scl to achieve rise times according to the smbus specifications. communication starts when the master signals a start condition, which is a high-to-low transition on sda, while scl is high. when the master has finished communicating, the master issues a stop condition, which is a low-to- high transition on sda, while scl is high. the bus is then free for another transmission. figure 15 and figure 16 show the timing diagram for signals on the smbus interface. the address byte, command byte, and data bytes are transmitted between the start and stop conditions. the sda state changes only while scl is low, except for the start and stop conditions. data is transmitted in 8-bit bytes and is sampled on the rising edge of scl. nine clock cycles are required to transfer each byte in or out of the device because either the master or the slave acknowledges the receipt of the correct byte during the ninth clock cycle. the BQ25710 supports the charger commands listed in table 4 .
32 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated programming (continued) (1) master to slave (2) s = start condition or repeated start condition (3) w = write bit (logic-low) (4) slave to master (shaded gray) (5) ack = acknowledge (logic-low) (6) p = stop condition 9.5.1.1 smbus write-word and read-word protocols table 4. write-word format s (1) (2) slave address (1) w (1) (3) ack (4) (5) command byte (1) ack (4) (5) low data byte (1) ack (4) (5) high data byte (1) ack (4) (5) p (1) (6) 7 bits 1b 1b 8 bits 1b 8 bits 1b 8 bits 1b msb lsb 0 0 msb lsb 0 msb lsb 0 msb lsb 0 (1) master to slave (2) s = start condition or repeated start condition (3) w = write bit (logic-low) (4) slave to master (shaded gray) (5) ack = acknowledge (logic-low) (6) r = read bit (logic-high) (7) nack = not acknowledge (logic-high) (8) p = stop condition table 5. read-word format s (1) (2) slave address (1) w (1) (3) ack (4) (5) command byte (1) ack (4) (5) s (1) (2) slave address (1) r (1) (6) ack (4) (5) low data byte (4) ack (1) (5) high data byte (4) nack (1) (7) p (1) (8) 7 bits 1b 1b 8 bits 1b 7 bits 1b 1b 8 bits 1b 8 bits 1b msb lsb 0 0 msb lsb 0 msb lsb 1 0 msb lsb 0 msb lsb 1 9.5.1.2 timing diagrams a = start condition h = lsb of data clocked into slave b = msb of address clocked into slave i = slave pulls smbdata line low c = lsb of address clocked into slave j = acknowledge clocked into master d = r/w bit clocked into slave k = acknowledge clock pulse e = slave pulls smbdata line low l = stop condition, data executed by slave f = acknowledge bit clocked into master m = new start condition g = msb of data clocked into slave figure 15. smbus write timing a b c d e f g h i j k l m t low t high smbclk smbdata t su:sta t hd:sta su:dat t t hd:dat hd:dat t t su:sto t buf
33 BQ25710 www.ti.com slusd20 ? july 2018 product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated a = start condition g = msb of data clocked into master b = msb of address clocked into slave h = lsb of data clocked into master c = lsb of address clocked into slave i = acknowledge clock pulse d = r/w bit clocked into slave j = stop condition e = slave pulls smbdata line low k = new start condition f = acknowledge bit clocked into master figure 16. smbus read timing 9.6 register map table 6. charger command summary smbus addr register name type description links 12h chargeoption0() r/w charge option 0 go 14h chargecurrent() r/w 7-bit charge current setting lsb 64 ma, range 0 ma - 8128 ma go 15h maxchargevoltage() r/w 12-bit charge voltage setting lsb 16 mv, default: 1s-4200mv, 2s-8400mv, 3s-12600mv, 4s-16800mv go 30h chargeoption1() r/w charge option 1 go 31h chargeoption2() r/w charge option 2 go 32h chargeoption3() r/w charge option 3 go 33h prochotoption0() r/w prochot option 0 go 34h prochotoption1() r/w prochot option 1 go 35h adcoption() r/w adc option go 20h chargerstatus() r charger status go 21h prochotstatus() r prochot status go 22h iin_dpm() r 7-bit input current limit in use lsb: 50 ma, range: 50 ma - 6400 ma go 23h adcvbus/psys() r 8-bit digital output of input voltage, 8-bit digital output of system power psys: full range: 3.06 v, lsb: 12 mv vbus: full range: 3.2 v - 19.52 v, lsb 64 mv go 24h adcibat() r 8-bit digital output of battery charge current, 8-bit digital output of battery discharge current ichg: full range 8.128 a, lsb 64 ma idchg: full range: 32.512 a, lsb: 256 ma go a b c d e f g h i j k t low t high smbclk smbdata t su:sta t t hd:sta su:dat hd:dat su:dat t t t su:sto t buf a = start condition e = slave pulls smbdata line low i = acknowledge clock pulse
34 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated register map (continued) table 6. charger command summary (continued) smbus addr register name type description links 25h adciincmpin() r 8-bit digital output of input current, 8-bit digital output of cmpin voltage por state - iin: full range: 12.75 a, lsb 50 ma cmpin: full range 3.06 v, lsb: 12 mv go 26h adcvsysvbat() r 8-bit digital output of system voltage, 8-bit digital output of battery voltage vsys: full range: 2.88 v - 19.2 v, lsb: 64 mv vbat: full range : 2.88 v - 19.2 v, lsb 64 mv go 3bh otgvoltage() r/w 12-bit otg voltage setting lsb 8 mv, range: 3000 mv ? 20800 mv go 3ch otgcurrent() r/w 7-bit otg output current setting lsb 50 ma, range: 0 a ? 6350 ma go 3dh inputvoltage() r/w 8-bit input voltage setting lsb 64 mv, range: 3200 mv ? 19520 mv go 3eh minsystemvoltage() r/w 6-bit minimum system voltage setting lsb: 256 mv, range: 1024 mv - 16182 mv default: 1s-3.584v, 2s-6.144v, 3s-9.216v, 4s- 12.288v go 3fh iin_host() r/w 6-bit input current limit set by host lsb: 50 ma, range: 50 ma - 6400 ma go feh manufacturerid() r manufacturer id - 0x0040h go ffh deviceid() r device id go
35 BQ25710 www.ti.com slusd20 ? july 2018 product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.6.1 setting charge and prochot options 9.6.1.1 chargeoption0 register ( smbus address = 12h) [reset = e60eh] figure 17. chargeoption0 register ( smbus address = 12h) [reset = e60eh] 15 14 13 12 11 10 9 8 en_lwpwr wdtmr_adj idpm_auto_ disable otg_on_ chrgok en_ooa pwm_freq ptm_ll_eff r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 reserved sys_short disable en_learn iadpt_gain ibat_gain en_ldo en_idpm chrg_inhibit r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 7. chargeoption0 register (smbus address = 12h) field descriptions smbus bit field type reset description 15 en_lwpwr r/w 1b low power mode enable 0b: disable low power mode. device in performance mode with battery only. the prochot, current/power monitor buffer and comparator follow register setting. 1b: enable low power mode. device in low power mode with battery only for lowest quiescent current. the ldo is off. the prochot, discharge current monitor buffer, power monitor buffer and independent comparator are disabled. adc is not available in low power mode. independent comparator can be enabled by setting either reg0x30()[14] or [13] to 1. < default at por > 14-13 wdtmr_adj r/w 11b watchdog timer adjust set maximum delay between consecutive smbus write of charge voltage or charge current command. if device does not receive a write on the reg0x15() or the reg0x14() within the watchdog time period, the charger will be suspended by setting the reg0x14() to 0 ma. after expiration, the timer will resume upon the write of reg0x14(), reg0x15() or reg0x12[14:13]. the charger will resume if the values are valid. 00b: disable watchdog timer 01b: enabled, 5 sec 10b: enabled, 88 sec 11b: enable watchdog timer, 175 sec < default at por > 12 idpm_auto_ disable r/w 0b idpm auto disable when cell_batpresz pin is low, the charger automatically disables the idpm function by setting en_idpm (reg0x12[1]) to 0. the host can enable idpm function later by writing en_idpm bit (reg0x12[1]) to 1. 0b: disable this function. idpm is not disabled when cell_batpresz goes low. < default at por > 1b: enable this function. idpm is disabled when cell_batpresz goes low. 11 otg_on_ chrgok r/w 0b add otg to chrg_ok drive chrg_ok to high when the device is in otg mode. 0b: disable < default at por > 1b: enable 10 en_ooa r/w 0b out-of-audio enable 0b: no limit of pfm burst frequency 1b: set minimum pfm burst frequency to above 25 khz to avoid audio noise < default at por >
36 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated table 7. chargeoption0 register (smbus address = 12h) field descriptions (continued) smbus bit field type reset description 9 pwm_freq r/w 1b switching frequency two converter switching frequencies. one for small inductor and the other for big inductor. recommend 800 khz with 2.2 h or 3.3 h, and 1.2 mhz with 1 h or 1.5 h. 0b: 1200 khz 1b: 800 khz < default at por > 8 low_ptm_ ripple r/w 1b ptm mode input voltage and current ripple reduction. 0b: disable 1b: enable < default at por > table 8. chargeoption0 register (smbus address = 12h) field descriptions smbus bit field type reset description 7 reserved r/w 0b reserved 6 sys_short_disable r/w 0b to disable the hiccup mode during the system short protection. 0b: when vsys is short to lower than 2.4v, the charger enters hiccup mode < default at por > 1b: the charger hiccup mode is disabled during system short fault 5 en_learn r/w 0b learn function allows the battery to discharge while the adapter is present. it calibrates the battery gas gauge over a complete discharge/charge cycle. when the battery voltage is below battery depletion threshold, the system switches back to adapter input by the host. when cell_batpresz pin is low, the device exits learn mode and this bit is set back to 0. 0b: disable learn mode < default at por > 1b: enable learn mode 4 iadpt_gain r/w 0b iadpt amplifier ratio the ratio of voltage on iadpt and voltage across acp and acn. 0b: 20 < default at por > 1b: 40 3 ibat_gain r/w 1b ibat amplifier ratio the ratio of voltage on ibat and voltage across srp and srn 0b: 8 1b: 16 < default at por > 2 en_ldo r/w 1b ldo mode enable when battery voltage is below minimum system voltage (reg0x3e()), the charger is in pre-charge with ldo mode enabled. 0b: disable ldo mode, batfet fully on. precharge current is set by battery pack internal resistor. the system is regulated by the maxchargevoltage register. 1b: enable ldo mode, precharge current is set by the chargecurrent register and clamped below 384 ma (2 cell ? 4 cell) or 2a (1 cell). the system is regulated by the minsystemvoltage register. < default at por > 1 en_idpm r/w 1b idpm enable host writes this bit to enable idpm regulation loop. when the idpm is disabled by the charger (refer to idpm_auto_disable), this bit goes low. 0b: idpm disabled 1b: idpm enabled < default at por > 0 chrg_inhibit r/w 0b charge inhibit when this bit is 0, battery charging will start with valid values in the maxchargevoltage register and the chargecurrent register. 0b: enable charge < default at por > 1b: inhibit charge
37 BQ25710 www.ti.com slusd20 ? july 2018 product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.6.1.2 chargeoption1 register ( smbus address = 30h) [reset = 0211h] figure 18. chargeoption1 register ( smbus address = 30h) [reset = 0211h] 15 14 13 12 11 10 9 8 en_ibat en_prochot_lpwr en_psys rsns_rac rsns_rsr psys_ratio ptm_pinsel r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 cmp_ref cmp_pol cmp_deg force_ latchoff en_ptm en_ship_ dchg auto_ wakeup_en r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 9. chargeoption1 register (smbus address = 30h) field descriptions smbus bit field type reset description 15 en_ibat r/w 0b ibat enable enable the ibat output buffer. in low power mode (reg0x12[15] = 1), ibat buffer is always disabled regardless of this bit value. 0b turn off ibat buffer to minimize iq < default at por > 1b: turn on ibat buffer 14-13 en_prochot _lpwr r/w 00b enable prochot during battery only low power mode with battery only, enable vsys in prochot with low power consumption. do not enable this function with adapter present. refer to prochot during low power mode for more details. 00b: disable low power prochot < default at por > 01b: reserved 10b: enable vsys low power prochot 11b: reserved 12 en_psys r/w 0b psys enable enable psys sensing circuit and output buffer (whole psys circuit). in low power mode (reg0x12[15] = 1), psys sensing and buffer are always disabled regardless of this bit value. 0b: turn off psys buffer to minimize iq < default at por > 1b: turn on psys buffer 11 rsns_rac r/w 0b input sense resistor rac 0b: 10 m < default at por > 1b: 20 m 10 rsns_rsr r/w 0b charge sense resistor rsr 0b: 10 m < default at por > 1b: 20 m 9 psys_ratio r/w 1b psys gain ratio of psys output current vs total input and battery power with 10-m sense resistor. 0b: 0.25 a/w 1b: 1 a/w < default at por > 8 ptm_pinsel r/w 0b select the ilim_hiz pin function 0b: charger enters hiz mode when pull low the ilim_hiz pin. < default at por > 1b: charger enters ptm when pull low the ilim_hiz pin.
38 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated table 10. chargeoption1 register (smbus address = 30h) field descriptions smbus bit field type reset description 7 cmp_ref r/w 0b independent comparator internal reference 0b: 2.3 v < default at por > 1b: 1.2 v 6 cmp_pol r/w 0b independent comparator output polarity 0b: when cmpin is above internal threshold, cmpout is low (internal hysteresis) < default at por > 1b: when cmpin is below internal threshold, cmpout is low (external hysteresis) 5-4 cmp_deg r/w 01b independent comparator deglitch time, only applied to the falling edge of cmpout (high low). 00b: independent comparator is disabled 01b: independent comparator is enabled with output deglitch time 1 s < default at por > 10b: independent comparator is enabled with output deglitch time of 2 ms 11b: independent comparator is enabled with output deglitch time of 5 sec 3 force_latchoff r/w 0b force power path off when independent comparator triggers, charger turns off q1 and q4 (same as disable converter) so that the system is disconnected from the input source. at the same time, chrg_ok signal goes to low to notify the system. 0b: disable this function < default at por > 1b: enable this function 2 en_ptm r/w 0b ptm enable register bit 0b: disable ptm. < default at por > 1b: enable ptm. 1 en_ship_dchg r/w 0b discharge srn for shipping mode when this bit is 1, discharge srn pin down below 3.8 v in 140 ms. when 140 ms is over, this bit is reset to 0. 0b: disable shipping mode < default at por > 1b: enable shipping mode 0 auto_wakeup_en r/w 1b auto wakeup enable when this bit is high, if the battery is below minimum system voltage (reg0x3e()), the device will automatically enable 128 ma charging current for 30 mins. when the battery is charged up above minimum system voltage, charge will terminate and the bit is reset to low. 0b: disable 1b: enable < default at por >
39 BQ25710 www.ti.com slusd20 ? july 2018 product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.6.1.3 chargeoption2 register ( smbus address = 31h) [reset = 02b7] figure 19. chargeoption2 register ( smbus address = 31h) [reset = 02b7] 15 14 13 12 11 10 9 8 pkpwr_tovld_deg en_pkpwr_ idpm en_pkpwr_ vsys pkpwr_ ovld_stat pkpwr_ relax_stat pkpwr_tmax[1:0] r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 en_extilim en_ichg _idchg q2_ocp acx_ocp en_acoc acoc_vth en_ _vth r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 11. chargeoption2 register (smbus address = 31h) field descriptions smbus bit field type reset description 15-14 pkpwr_ tovld_deg r/w 00b input overload time in peak power mode 00b: 1 ms < default at por > 01b: 2 ms 10b: 10 ms 11b: 20 ms 13 en_pkpwr_idpm r/w 0b enable peak power mode triggered by input current overshoot if reg0x31[13:12] are 00b, peak power mode is disabled. upon adapter removal, the bits are reset to 00b. 0b: disable peak power mode triggered by input current overshoot < default at por > 1b: enable peak power mode triggered by input current overshoot. 12 en_pkpwr_vsys r/w 0b enable peak power mode triggered by system voltage under-shoot if reg0x31[13:12] are 00b, peak power mode is disabled. upon adapter removal, the bits are reset to 00b. 0b: disable peak power mode triggered by system voltage under-shoot < default at por > 1b: enable peak power mode triggered by system voltage under-shoot. 11 pkpwr_ ovld_stat r/w 0b indicator that the device is in overloading cycle. write 0 to get out of overloading cycle. 0b: not in peak power mode. < default at por > 1b: in peak power mode. 10 pkpwr_ relax_stat r/w 0b indicator that the device is in relaxation cycle. write 0 to get out of relaxation cycle. 0b: not in relaxation cycle. < default at por > 1b: in relaxation mode. 9-8 pkpwr_ tmax[1:0] r/w 10b peak power mode overload and relax cycle time. when reg0x31[15:14] is programmed longer than reg0x31[9:8], there is no relax time. 00b: 5 ms 01b: 10 ms 10b: 20 ms < default at por > 11b: 40 ms
40 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated table 12. chargeoption2 register (smbus address = 31h) field descriptions smbus bit field type reset description 7 en_extilim r/w 1b enable ilim_hiz pin to set input current limit 0b: input current limit is set by reg0x3f. 1b: input current limit is set by the lower value of ilim_hiz pin and reg0x3f. < default at por > 6 en_ichg _idchg r/w 0b 0b: ibat pin as discharge current. < default at por > 1b: ibat pin as charge current. 5 q2_ocp r/w 1b q2 ocp threshold by sensing q2 vds 0b: 210 mv 1b: 150 mv < default at por > 4 acx_ocp r/w 1b input current ocp threshold by sensing acp-acn. 0b: 280 mv 1b: 150 mv < default at por > 3 en_acoc r/w 0b acoc enable input overcurrent (acoc) protection by sensing the voltage across acp and acn. upon acoc (after 100- s blank-out time), converter is disabled. 0b: disable acoc < default at por > 1b: acoc threshold 133% or 200% ilim2 2 acoc_vth r/w 1b acoc limit set mosfet ocp threshold as percentage of idpm with current sensed from r ac. 0b: 133% of ilim2 1b: 200% of ilim2 < default at por > 1 en_batoc r/w 1b batoc enable battery discharge overcurrent (batoc) protection by sensing the voltage across srn and srp. upon batoc, converter is disabled. 0b: disable batoc 1b: batoc threshold 133% or 200% prochot idchg < default at por > 0 batoc_vth r/w 1b set battery discharge overcurrent threshold as percentage of prochot battery discharge current limit. 0b: 133% of prochot idchg 1b: 200% of prochot idchg < default at por >
41 BQ25710 www.ti.com slusd20 ? july 2018 product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.6.1.4 chargeoption3 register ( smbus address = 32h) [reset = 0030h] figure 20. chargeoption3 register ( smbus address = 32h) [reset = 0030h] 15 14 13 12 11 10 9 8 en_hiz reset_reg reset_ vindpm en_otg en_ico mode reserved r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 reserved en_cons vap otg_vap _mode il_avg otg_range _low batfetoff_ hiz psys_otg_ idchg r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 13. chargeoption3 register (smbus address = 32h) field descriptions smbus bit field type reset description 15 en_hiz r/w 0b device hi-z mode enable when the charger is in hi-z mode, the device draws minimal quiescent current. with vbus above uvlo. regn ldo stays on, and system powers from battery. 0b: device not in hi-z mode < default at por > 1b: device in hi-z mode 14 reset_reg r/w 0b reset registers all the registers go back to the default setting except the vindpm register. 0b: idle < default at por > 1b: reset all the registers to default values. after reset, this bit goes back to 0. 13 reset_vindpm r/w 0b reset vindpm threshold 0b: idle 1b: converter is disabled to measure vindpm threshold. after vindpm measurement is done, this bit goes back to 0 and converter starts. 12 en_otg r/w 0b otg mode enable enable device in otg mode when en_otg pin is high. 0b: disable otg < default at por > 1b: enable otg mode to supply vbus from battery. 11 en_ico_mode r/w 0b enable ico algorithm 0b: disable ico algorithm. < default at por > 1b: enable ico algorithm. 10-8 reserved r/w 000b reserved table 14. chargeoption3 register (smbus address = 32h) field descriptions smbus bit field type reset description 7 reserved r/w 0b reserved 6 en_con_vap r/w 0b enable the conservative vap mode. 0b: disabled < default at por > 1b: enabled 5 otg_vap_mode r/w 1b the selection of the external otg/vap pin control. 0b: the external otg/vap pin controls the en/dis vap mode 1b: the external otg/vap pin controls the en/dis otg mode < default at por >
42 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated table 14. chargeoption3 register (smbus address = 32h) field descriptions (continued) smbus bit field type reset description 4-3 il_avg r/w 10b 4 levels inductor average current clamp. 00b: 6a 01b: 10a 10b: 15a < default at por > 11b: disabled 2 otg_range_low r/w 0b selection of the different otg ouput voltage range. 0b: votg high range 4.28 v - 20.8 v < default at por > 1b: votg low range 3 v - 19.52 v 1 batfetoff_ hiz r/w 0b control batfet during hiz mode. 0b: batfet on during hi-z < default at por > 1b: batfet off during hi-z 0 psys_otg_ idchg r/w 0b psys function during otg mode. 0b: psys as battery discharge power minus otg output power < default at por > 1b: psys as battery discharge power only
43 BQ25710 www.ti.com slusd20 ? july 2018 product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.6.1.5 prochotoption0 register ( smbus address = 33h) [reset = 04a61h] figure 21. prochotoption0 register ( smbus address = 33h) [reset = 04a61h] 15-11 10-9 8 ilim2_vth icrit_deg prochot_ vdpm_80_90 r/w r/w r/w 7-4 3-2 1 0 vsys_th1 vsys_th2 inom_deg lower_ prochot _vdpm r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 15. prochotoption0 register (smbus address = 33h) field descriptions smbus bit field type reset description 15-11 ilim2_vth r/w 01001b i lim2 threshold 5 bits, percentage of idpm in 0x3fh. measure current between acp and acn. trigger when the current is above this threshold: 00001b - 11001b: 110% - 230%, step 5% 11010b - 11110b: 250% - 450%, step 50% 11111b: out of range (ignored) default 150%, or 01001 10-9 icrit_deg r/w 01b icrit deglitch time icrit threshold is set to be 110% of ilim2 . typical icrit deglitch time to trigger prochot. 00b: 15 s 01b: 100 s < default at por > 10b: 400 s (max 500 us) 11b: 800 s (max 1 ms) 8 prochot_ vdpm_80_90 r/w 0b lower threshold of the prochot_vdpm comparator when reg0x33[0]=1, the threshold of the prochot_vdpm comparator is determined by this bit setting. 0b: 80% of vindpm threshold < default at por > . 1b: 90% of vindpm threshold table 16. prochotoption0 register (smbus address = 33h) field descriptions smbus bit field type reset description 7-4 vsys_th1 r/w 0110b vsys threshold to trigger discharging vbus in vap mode. measure on vsys with fixed 5- s deglitch time. trigger when sys pin voltage is below the thresholds. 2s - 4s battery 0000b - 1111b: 5.9 v - 7.4v with 0.1 v step size. 1s battery 0000b - 0111b: 3.1 v - 3.8 v with 0.1 v step size. 1000b - 1111b: 3.1 v - 3.8 v with 0.1 v step size.
44 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated table 16. prochotoption0 register (smbus address = 33h) field descriptions (continued) smbus bit field type reset description 3-2 vsys_th2 r/w 01b vsys threshold to assert /prochot_vsys. measure on vsys with fixed 5- s deglitch time. trigger when sys pin voltage is below the thresholds. 2s - 4s battery 00b: 5.9v; 01b: 6.2v < default at por > ; 10b: 6.5v; 11b: 6.8v. 1s battery 00b: 3.1v; 01b: 3.3v < default at por > ; 10b: 3.5v; 11b: 3.7v. 1 inom_deg r/w 0b inom deglitch time inom is always 10% above idpm in 0x3fh. measure current between acp and acn. trigger when the current is above this threshold. 0b: 1 ms (must be max) < default at por > 1b: 50 ms (max 60 ms) 0 lower_ prochot _vdpm r/w 0b enable the lower threshold of the prochot_vdpm comparator 0b: the threshold of the prochot_vdpm comparator follows the same vindpm reg0x3d() setting. 1b: the threshold of the prochot_vdpm comparator is lower and determined by reg0x33[8] setting. < default at por >
45 BQ25710 www.ti.com slusd20 ? july 2018 product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.6.1.6 prochotoption1 register ( smbus address = 34h) [reset = 81a0h] figure 22. prochotoption1 register ( smbus address = 34h) [reset = 81a0h] 15-10 9-8 idchg_vth idchg_deg r/w r/w 7 6 5 4 3 2 1 0 pp_vdpm prochot_pr ofile_ic pp_icrit pp_inom pp_idchg pp_vsys pp_batpres pp_acok r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset when the reg0x 34h[7:0] are set to be disabled, the prochot event associated with that bit will not be reported in the prochot status register reg0x 21h[7:0] any more, and the prochot pin will not be pulled low any more if the event happens. table 17. prochotoption1 register (smbus address = 34h) field descriptions smbus bit field type reset description 15-10 idchg_vth r/w 100000b idchg threshold 6 bit, range, range 0 a to 32256 ma, step 512 ma. there is a 128 ma offset measure current between srn and srp. trigger when the discharge current is above the threshold. if the value is programmed to 000000b prochot is always triggered. default: 16384 ma or 100000b 9-8 idchg_deg r/w 01b idchg deglitch time 00b: 1.6 ms 01b: 100 s < default at por > 10b: 6 ms 11b: 12 ms table 18. prochotoption1 register (smbus address = 34h) field descriptions smbus bit field type reset description 7 prochot _profile_vdpm r/w 1b prochot profile when all the reg0x34[7:0] bits are 0, prochot function is disabled. bit7 pp_vdpm detects vbus voltage 0b: disable < default at por > 1b: enable 6 prochot _profile_comp r/w 0b 0b: disable < default at por > 1b: enable 5 prochot _profile_icrit r/w 1b 0b: disable 1b: enable < default at por > 4 prochot _profile_inom r/w 0b 0b: disable < default at por > 1b: enable 3 prochot _profile_idchg r/w 0b 0b: disable < default at por > 1b: enable 2 prochot _profile_vsys r/w 0b 0b: disable < default at por > 1b: enable
46 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated table 18. prochotoption1 register (smbus address = 34h) field descriptions (continued) smbus bit field type reset description 1 prochot _profile_batpres r/w 0b 0b: disable < default at por > 1b: enable (one-shot falling edge triggered) if batpres is enabled in prochot after the battery is removed, it will immediately send out one-shot prochot pulse. 0 prochot _profile_acok r/w 0b 0b: disable < default at por > 1b: enable chargeoption0[15] = 0 to assert prochot pulse after adapter removal. if prochot_profile_acok is enabled in prochot after the adapter is removed, it will be pulled low.
47 BQ25710 www.ti.com slusd20 ? july 2018 product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.6.1.7 adcoption register ( smbus address = 35h) [reset = 2000h] figure 23. adcoption register ( smbus address = 35h) [reset = 2000h] 15 14 13 12-8 adc_conv adc_start adc_ fullscale reserved r/w r/w r/w r/w 7 6 5 4 3 2 1 0 en_adc_ cmpin en_adc_ vbus en_adc_ psys en_adc_ iin en_adc_ idchg en_adc_ ichg en_adc_ vsys en_adc_ vbat r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset the adc registers are read in the following order: vbat, vsys, ichg, idchg, iin, psys, vbus, cmpin. adc is disabled in low power mode. before enabling adc, low power mode should be disabled first. table 19. adcoption register (smbus address = 35h) field descriptions smbus bit field type reset description 15 adc_conv r/w 0b typical adc conversion time is 10 ms. 0b: one-shot update. do one set of conversion updates to registers reg0x23(), reg0x24(), reg0x25(), and reg0x26() after adc_start = 1. 1b: continuous update. do a set of conversion updates to registers reg0x23(), reg0x24(), reg0x25(), and reg0x26() every 1 sec. 14 adc_start r/w 0b 0b: no adc conversion 1b: start adc conversion. after the one-shot update is complete, this bit automatically resets to zero 13 adc_ fullscale r/w 1b adc input voltage range. when input voltage is below 5 v, or battery is 1s, full scale 2.04 v is recommended. 0b: 2.04 v 1b: 3.06 v < default at por > 12-8 reserved r/w 00000b reserved table 20. adcoption register (smbus address = 35h) field descriptions smbus bit field type reset description 7 en_adc_cmpin r/w 0b 0b: disable < default at por > 1b: enable 6 en_adc_vbus r/w 0b 0b: disable < default at por > 1b: enable 5 en_adc_psys r/w 0b 0b: disable < default at por > 1b: enable 4 en_adc_iin r/w 0b 0b: disable < default at por > 1b: enable 3 en_adc_idchg r/w 0b 0b: disable < default at por > 1b: enable 2 en_adc_ichg r/w 0b 0b: disable < default at por > 1b: enable 1 en_adc_vsys r/w 0b 0b: disable < default at por > 1b: enable 0 en_adc_vbat r/w 0b 0b: disable < default at por > 1b: enable
48 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.6.2 charge and prochot status 9.6.2.1 chargerstatus register ( smbus address = 20h) [reset = 0000h] figure 24. chargerstatus register ( smbus address = 20h) [reset = 0000h] 15 14 13 12 11 10 9 8 ac_stat ico_done in_vap in_vindpm in_iindpm in_fchrg in_pchrg in_otg r r r r r r r r 7 6 5 4 3 2 1 0 fault acov fault batoc fault acoc sysovp _stat fault sys _short fault latchoff fault_otg _ovp fault_otg _ocp r r r r/w r/w r r r legend: r/w = read/write; r = read only; -n = value after reset table 21. chargerstatus register (smbus address = 20h) field descriptions smbus bit field type reset description 15 ac_stat r 0b input source status, same as chrg_ok bit 0b: input not present 1b: input is present 14 ico_done r 0b after the ico routine is successfully executed, the bit goes 1. 0b: ico is not complete 1b: ico is complete 13 in_vap r 0b 0b: charger is not operated in vap mode 1b: charger is operated in vap mode 12 in_vindpm r 0b 0b: charger is not in vindpm during forward mode, or voltage regulation during otg mode 1b: charger is in vindpm during forward mode, or voltage regulation during otg mode 11 in_iindpm r 0b 0b: charger is not in iindpm 1b: charger is in iindpm 10 in_fchrg r 0b 0b: charger is not in fast charge 1b: charger is in fast charger 9 in_pchrg r 0b 0b: charger is not in pre-charge 1b: charger is in pre-charge 8 in_otg r 0b 0b: charger is not in otg 1b: charge is in otg table 22. chargerstatus register (smbus address = 20h) field descriptions smbus bit field type reset description 7 fault acov r 0b the faults are latched until a read from host. 0b: no fault 1b: acov 6 fault batoc r 0b the faults are latched until a read from host. 0b: no fault 1b: batoc 5 fault acoc r 0b the faults are latched until a read from host. 0b: no fault 1b: acoc
49 BQ25710 www.ti.com slusd20 ? july 2018 product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated table 22. chargerstatus register (smbus address = 20h) field descriptions (continued) smbus bit field type reset description 4 sysovp_stat r/w 0b sysovp status and clear when the sysovp occurs, this bit is high. during the sysovp, the converter is disabled. after the sysovp is removed, the user must write a 0 to this bit or unplug the adapter to clear the sysovp condition to enable the converter again. 0b: not in sysovp < default at por > 1b: in sysovp. when sysovp is removed, write 0 to clear the sysovp latch. 3 fault sys_short r/w 0b the fault is latched until a clear from host by writing this bit to 0. 0b: no fault < default at por > 1b: when sys is lower than 2.4v, then 7 times restart tries are failed. 2 fault latchoff r 0b the faults are latched until a read from host. 0b: no fault 1b: latch off (reg0x30[3]) 1 fault_otg_ovp r 0b the faults are latched until a read from host. 0b: no fault 1b: otg ovp 0 fault_otg_uvp r 0b the faults are latched until a read from host. 0b: no fault 1b: otg uvp
50 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.6.2.2 prochotstatus register ( smbus address = 21h) [reset = 0h] figure 25. prochotstatus register ( smbus address = 21h) [reset = 0h] 15 14 13 12 11 10 9 8 reserved en_prochot _exit prochot_width prochot _clear reserved stat_vap _fail stat_exit _vap r r/w r/w r/w r r/w r/w 7 6 5 4 3 2 1 0 stat_vdpm stat_comp stat_icrit stat_inom stat_idchg stat_vsys stat_bat _removal stat_adpt _removal r/w r r r r r r r legend: r/w = read/write; r = read only; -n = value after reset table 23. prochotstatus register (smbus address = 21h) field descriptions smbus bit field type reset description 15 reserved r 0b reserved 14 en_prochot _exit r/w 0b prochot pulse extension enable. when pulse extension is enabled, keep the prochot pin voltage low until host writes reg0x21[11] = 0. 0b: disable pulse extension < default at por > 1b: enable pulse extension 13-12 prochot _width r/w 10b prochot pulse width minimum prochot pulse width when reg0x21[14] = 0 00b: 100 us 01b: 1 ms 10b: 10 ms < default at por > 11b: 5s 11 prochot _clear r/w 1b prochot pulse clear. clear prochot pulse when 0x21[14] = 1. 0b: clear prochot pulse and drive prochot pin high 1b: idle < default at por > 10 reserved r 0b reserved 9 stat_vap_fail r/w 0b this status bit reports a failure to load vbus 7 consecutive times in vap mode, which indicates the battery voltage might be not high enough to enter vap mode, or the vap loading current settings are too high. 0b: not is vap failure < default at por > 1b: in vap failure, the charger exits vap mode, and latches off until the host writes this bit to 0. 8 stat_exit_vap r/w 0b when the charger is operated in vap mode, it can exit vap by either being disabled through host, or there is any charger faults. 0b: prochot_exit_vap is not active < default at por > 1b: prochot_exit_vap is active, prochot pin is low until host writes this status bit to 0. table 24. prochotstatus register (smbus address = 21h) field descriptions smbus bit field type reset description 7 stat_vdpm r/w 0b 0b: not triggered 1b: triggered 6 stat_comp r 0b 0b: not triggered 1b: triggered
51 BQ25710 www.ti.com slusd20 ? july 2018 product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated table 24. prochotstatus register (smbus address = 21h) field descriptions (continued) smbus bit field type reset description 5 stat_icrit r 0b 0b: not triggered 1b: triggered 4 stat_inom r 0b 0b: not triggered 1b: triggered 3 stat_idchg r 0b 0b: not triggered 1b: triggered 2 stat_vsys r 0b 0b: not triggered 1b: triggered 1 stat_battery_removal r 0b 0b: not triggered 1b: triggered 0 stat_adapter_removal r 0b 0b: not triggered 1b: triggered
52 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.6.3 chargecurrent register ( smbus address = 14h) [reset = 0000h] to set the charge current, write a 16-bit chargecurrent() command (reg0x 14h()) using the data format listed in figure 26 , table 25 , and table 26 . with 10-m sense resistor, the charger provides charge current range of 64 ma to 8.128 a, with a 64-ma step resolution. upon por, chargecurrent() is 0 a. any conditions for chrg_ok low except acov will reset chargecurrent() to zero. cell_batpresz going low (battery removal) will reset the chargecurrent() register to 0 a. charge current is not reset in acoc, tshut, power path latch off (reg0x30[1]), and sysovp. a 0.1- f capacitor between srp and srn for differential mode filtering is recommended; an optional 0.1- f capacitor between srn and ground, and an optional 0.1- f capacitor between srp and ground for common mode filtering. meanwhile, the capacitance on srp should not be higher than 0.1 f in order to properly sense the voltage across srp and srn for cycle-by-cycle current detection. the srp and srn pins are used to sense voltage drop across rsr with default value of 10 m . however, resistors of other values can also be used. for a larger sense resistor, a larger sense voltage is given, and a higher regulation accuracy; but, at the expense of higher conduction loss. a current sensing resistor value no more than 20 m is suggested. figure 26. chargecurrent register with 10-m sense resistor ( smbus address = 14h) [reset = 0h] 15 14 13 12 11 10 9 8 reserved charge current, bit 6 charge current, bit 5 charge current, bit 4 charge current, bit 3 charge current, bit 2 r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 charge current, bit 1 charge current, bit 0 reserved reserved r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 25. charge current register (14h) with 10-m sense resistor (smbus address = 14h) field descriptions smbus bit field type reset description 15-13 reserved r/w 000b not used. 1 = invalid write. 12 charge current, bit 6 r/w 0b 0 = adds 0 ma of charger current. 1 = adds 4096 ma of charger current. 11 charge current, bit 5 r/w 0b 0 = adds 0 ma of charger current. 1 = adds 2048 ma of charger current. 10 charge current, bit 4 r/w 0b 0 = adds 0 ma of charger current. 1 = adds 1024 ma of charger current. 9 charge current, bit 3 r/w 0b 0 = adds 0 ma of charger current. 1 = adds 512 ma of charger current. 8 charge current, bit 2 r/w 0b 0 = adds 0 ma of charger current. 1 = adds 256 ma of charger current. table 26. charge current register (14h) with 10-m sense resistor (smbus address = 14h) field descriptions smbus bit field type reset description 7 charge current, bit 1 r/w 0b 0 = adds 0 ma of charger current. 1 = adds 128 ma of charger current. 6 charge current, bit 0 r/w 0b 0 = adds 0 ma of charger current. 1 = adds 64 ma of charger current.
53 BQ25710 www.ti.com slusd20 ? july 2018 product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated table 26. charge current register (14h) with 10-m sense resistor (smbus address = 14h) field descriptions (continued) smbus bit field type reset description 5-0 reserved r/w 000000b not used. value ignored. 9.6.3.1 battery pre-charge current clamp during pre-charge, batfet works in linear mode or ldo mode (default reg0x 12[2] = 1). for 2-4 cell battery, the system is regulated at minimum system voltage in reg0x 3e() and the pre-charge current is clamped at 384 ma. for 1 cell battery, the pre-charge to fast charge threshold is 3 v, and the pre-charge current is clamped at 384 ma. however, the batfet stays in ldo mode operation till battery voltage is above minimum system voltage (~3.6 v). during battery voltage from 3 v to 3.6 v, the fast charge current is clamped at 2 a.
54 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.6.4 maxchargevoltage register ( smbus address = 15h) [reset value based on cell_batpresz pin setting] to set the output charge voltage, write a 16-bit chargevoltage register command (reg0x 15()) using the data format listed in figure 27 , table 27 , and table 28 . the charger provides charge voltage range from 1.024 v to 19.200 v, with 8-mv step resolution. any write below 1.024 v or above 19.200 v is ignored. upon por, reg0x 15() is by default set as 4200 mv for 1 s, 8400 mv for 2 s, 12600 mv for 3 s or 16800 mv for 4 s. after chrg_ok goes high, the charge will start when the host writes the charging current to reg0x 14(), the default charging voltage is used if reg0x 15() is not programmed. if the battery is different from 4.2 v/cell, the host has to write to reg0x 15() before reg0x 14() for correct battery voltage setting. writing reg0x 15() to 0 will set reg0x 15() to the default value based on cell_batpresz pin, and force reg0x 14() to zero to disable charge. the srn pin senses the battery voltage for voltage regulation and should be connected as close to the battery as possible, and directly place a decoupling capacitor (0.1 f recommended) as close to the device as possible to decouple high frequency noise. figure 27. maxchargevoltage register ( smbus address = 15h) [reset value based on cell_batpresz pin setting] 15 14 13 12 11 10 9 8 reserved max charge voltage, bit 11 max charge voltage, bit 10 max charge voltage, bit 9 max charge voltage, bit 8 max charge voltage, bit 7 max charge voltage, bit 6 max charge voltage, bit 5 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 max charge voltage, bit 4 max charge voltage, bit 3 max charge voltage, bit 2 max charge voltage, bit 1 max charge voltage, bit 1 reserved r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 27. maxchargevoltage register (smbus address = 15h) field descriptions smbus bit field type reset description 15 reserved r/w 0b not used. 1 = invalid write. 14 max charge voltage, bit 11 r/w 0b 0 = adds 0 mv of charger voltage. 1 = adds 16384 mv of charger voltage. 13 max charge voltage, bit 10 r/w 0b 0 = adds 0 mv of charger voltage. 1 = adds 8192 mv of charger voltage 12 max charge voltage, bit 9 r/w 0b 0 = adds 0 mv of charger voltage. 1 = adds 4096 mv of charger voltage. 11 max charge voltage, bit 8 r/w 0b 0 = adds 0 mv of charger voltage. 1 = adds 2048 mv of charger voltage. 10 max charge voltage, bit 7 r/w 0b 0 = adds 0 mv of charger voltage. 1 = adds 1024 mv of charger voltage. 9 max charge voltage, bit 6 r/w 0b 0 = adds 0 mv of charger voltage. 1 = adds 512 mv of charger voltage. 8 max charge voltage, bit 5 r/w 0b 0 = adds 0 mv of charger voltage. 1 = adds 256 mv of charger voltage. table 28. maxchargevoltage register (smbus address = 15h) field descriptions smbus bit field type reset description 7 max charge voltage, bit 4 r/w 0b 0 = adds 0 mv of charger voltage. 1 = adds 128 mv of charger voltage.
55 BQ25710 www.ti.com slusd20 ? july 2018 product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated table 28. maxchargevoltage register (smbus address = 15h) field descriptions (continued) smbus bit field type reset description 6 max charge voltage, bit 3 r/w 0b 0 = adds 0 mv of charger voltage. 1 = adds 64 mv of charger voltage. 5 max charge voltage, bit 2 r/w 0b 0 = adds 0 mv of charger voltage. 1 = adds 32 mv of charger voltage. 4 max charge voltage, bit 1 r/w 0b 0 = adds 0 mv of charger voltage. 1 = adds 16 mv of charger voltage. 3 max charge voltage, bit 0 r/w 0b 0 = adds 0 mv of charger voltage. 1 = adds 8 mv of charger voltage. 2-0 reserved r/w 000b not used. value ignored.
56 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.6.5 minsystemvoltage register ( smbus address = 3eh) [reset value based on cell_batpresz pin setting] to set the minimum system voltage, write a 16-bit minsystemvoltage register command (reg0x 3e()) using the data format listed in figure 28 , table 29 , and table 30 . the charger provides minimum system voltage range from 1.024 v to 16.128 v, with 256-mv step resolution. any write below 1.024 v or above 16.128 v is ignored. upon por, the minsystemvoltage register is 3.584 v for 1 s, 6.144 v for 2 s and 9.216 v for 3 s, and 12.288 v for 4 s. figure 28. minsystemvoltage register ( smbus address = 3eh) [reset value based on cell_batpresz pin setting] 15 14 13 12 11 10 9 8 reserved min system voltage, bit 5 min system voltage, bit 4 min system voltage, bit 3 min system voltage, bit 2 min system voltage, bit 1 min system voltage, bit 0 r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 reserved r/w legend: r/w = read/write; r = read only; -n = value after reset table 29. minsystemvoltage register (smbus address = 3eh) field descriptions smbus bit field type reset description 15-14 reserved r/w 00b not used. 1 = invalid write. 13 min system voltage, bit 5 r/w 0b 0 = adds 0 mv of system voltage. 1 = adds 8192 mv of system voltage. 12 min system voltage, bit 4 r/w 0b 0 = adds 0 mv of system voltage. 1 = adds 4096mv of system voltage. 11 min system voltage, bit 3 r/w 0b 0 = adds 0 mv of system voltage. 1 = adds 2048 mv of system voltage. 10 min system voltage, bit 2 r/w 0b 0 = adds 0 mv of system voltage. 1 = adds 1024 mv of system voltage. 9 min system voltage, bit 1 r/w 0b 0 = adds 0 mv of system voltage. 1 = adds 512 mv of system voltage. 8 min system voltage, bit 0 r/w 0b 0 = adds 0 mv of system voltage. 1 = adds 256 mv of system voltage. table 30. minsystemvoltage register (smbus address = 3eh) field descriptions smbus bit field type reset description 7-0 reserved r/w 0000000 0b not used. value ignored. 9.6.5.1 system voltage regulation the device employs narrow vdc architecture (nvdc) with batfet separating system from battery. the minimum system voltage is set by reg0x 3e(). even with a deeply depleted battery, the system is regulated above the minimum system voltage with batfet. when the battery is below minimum system voltage setting, the batfet operates in linear mode (ldo mode), and the system is regulated above the minimum system voltage setting. as the battery voltage rises above the minimum system voltage, batfet is fully on when charging or in supplement mode and the voltage difference between the system and battery is the vds of batfet. system voltage is regulated 160 mv above battery voltage when batfet is off (no charging or no supplement current). when batfet is removed, the system node vsys is shorted to srp. before the converter starts operation, ldo mode needs to be disabled. the following sequence is required to configure charger without batfet.
57 BQ25710 www.ti.com slusd20 ? july 2018 product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated 1. before adapter plugs in, put the charger into hiz mode. (either pull pin 6 ilim_hiz to ground, or set reg0x to 1) 2. set 0x to 0 to disable ldo mode. 3. set 0x30[0] to 0 to disable auto-wakeup mode. 4. check if battery voltage is properly programmed (reg0x) 5. set pre-charge/charge current (reg0x) 6. put the device out of hiz mode. (release ilim_hiz from ground and set reg0x=0). in order to prevent any accidental sw mistakes, the host sets low input current limit (a few hundred milliamps) when device is out of hiz. 9.6.6 input current and input voltage registers for dynamic power management the charger supports dynamic power management (dpm). normally, the input power source provides power for the system load or to charge the battery. when the input current exceeds the input current setting, or the input voltage falls below the input voltage setting, the charger decreases the charge current to provide priority to the system load. as the system current rises, the available charge current drops accordingly towards zero. if the system load keeps increasing after the charge current drops down to zero, the system voltage starts to drop. as the system voltage drops below the battery voltage, the battery will discharge to supply the heavy system load. 9.6.6.1 input current registers to set the maximum input current limit, write a 16-bit iin_host register command (reg0x 3f()) using the data format listed in table 31 and table 32 . when using a 10-m sense resistor, the charger provides an input- current limit range of 50 ma to 6400 ma, with 50-ma resolution. the default current limit is 3.3 a. due to the usb current setting requirement, the register setting specifies the maximum current instead of the typical current. upon adapter removal, the input current limit is reset to the default value of 3.3 a. the register offset is 50 ma. with code 0, the input current limit is 50 ma. the acp and acn pins are used to sense r ac with the default value of 10 m . for a 20-m sense resistor, a larger sense voltage is given and a higher regulation accuracy, but at the expense of higher conduction loss. instead of using the internal dpm loop, the user can build up an external input current regulation loop and have the feedback signal on the ilim_hiz pin. (2) in order to disable ilim_hiz pin, the host can write to 0x 31[7] to disable ilim_hiz pin, or pull ilim_hiz pin above 4.0 v. ( ) ilim _ hiz acp acn dpm ac v 1v 40 v v 1 40 i r = + - = +
58 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.6.6.1.1 iin_host register with 10-m sense resistor ( smbus address = 3fh) [reset = 4000h] the register offset is 50 ma. with code 0, the input current limit readback is 50 ma. figure 29. iin_host register with 10-m sense resistor ( smbus address = 3fh) [reset = 4100h] 15 14 13 12 11 10 9 8 reserved input current set by host, bit 6 input current set by host, bit 5 input current set by host, bit 4 input current set by host, bit 3 input current set by host, bit 2 input current set by host, bit 1 input current set by host, bit 0 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 reserved r legend: r/w = read/write; r = read only; -n = value after reset table 31. iin_host register with 10-m sense resistor (smbus address = 3fh) field descriptions smbus bit field type reset description 15 reserved r/w 0b not used. 1 = invalid write. 14 input current set by host, bit 6 r/w 1b 0 = adds 0 ma of input current. 1 = adds 3200 ma of input current. 13 input current set by host, bit 5 r/w 0b 0 = adds 0 ma of input current. 1 = adds 1600 ma of input current. 12 input current set by host, bit 4 r/w 0b 0 = adds 0 ma of input current. 1 = adds 800 ma of input current. 11 input current set by host, bit 3 r/w 0b 0 = adds 0 ma of input current. 1 = adds 400 ma of input current. 10 input current set by host, bit 2 r/w 0b 0 = adds 0 ma of input current. 1 = adds 200 ma of input current. 9 input current set by host, bit 1 r/w 0b 0 = adds 0 ma of input current. 1 = adds 100 ma of input current. 8 input current set by host, bit 0 r/w 0b 0 = adds 0 ma of input current. 1 = adds 50 ma of input current. table 32. iin_host register with 10-m sense resistor (smbus address = 3fh) field descriptions smbus bit field type reset description 7-0 reserved r 0000000 0b not used. value ignored.
59 BQ25710 www.ti.com slusd20 ? july 2018 product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.6.6.1.2 iin_dpm register with 10-m sense resistor ( smbus address = 022h) [reset = 0h] iin_dpm register reflects the actual input current limit programmed in the register, either from host or from ico. after ico, the current limit used by dpm regulation may differ from the iin_host register settings. the actual dpm limit is reported in reg0x 22(). the register offset is 50 ma. with code 0, the input current limit read-back is 50 ma. figure 30. iin_dpm register with 10-m sense resistor ( smbus address = 022h) [reset = 0h] 15 14 13 12 11 10 9 8 reserved input current in dpm, bit 6 input current in dpm, bit 5 input current in dpm, bit 4 input current in dpm, bit 3 input current in dpm, bit 2 input current in dpm, bit 1 input current in dpm, bit 0 r r r r r r r r 7 6 5 4 3 2 1 0 reserved r legend: r/w = read/write; r = read only; -n = value after reset table 33. iin_dpm register with 10-m sense resistor (smbus address = 022h) field descriptions smbus bit field type reset description 15 reserved r 0b not used. 1 = invalid write. 14 input current in dpm, bit 6 r 0b 0 = adds 0 ma of input current. 1 = adds 3200 ma of input current. 13 input current in dpm, bit 5 r 0b 0 = adds 0 ma of input current. 1 = adds 1600 ma of input current. 12 input current in dpm, bit 4 r 0b 0 = adds 0 ma of input current. 1 = adds 800ma of input current 11 input current in dpm, bit 3 r 0b 0 = adds 0 ma of input current. 1 = adds 400 ma of input current. 10 input current in dpm, bit 2 r 0b 0 = adds 0 ma of input current. 1 = adds 200 ma of input current. 9 input current in dpm, bit 1 r 0b 0 = adds 0 ma of input current. 1 = adds 100 ma of input current. 8 input current in dpm, bit 0 r 0b 0 = adds 0 ma of input current. 1 = adds 50 ma of input current. table 34. iin_dpm register with 10-m sense resistor (smbus address = 022h) field descriptions smbus bit field type reset description 7-0 reserved r 00000000b not used. value ignored.
60 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.6.6.1.3 inputvoltage register ( smbus address = 3dh) [reset = vbus-1.28v] to set the input voltage limit, write a 16-bit inputvoltage register command (reg0x 3d()) using the data format listed in figure 31 , table 35 , and table 36 . if the input voltage drops more than the inputvoltage register allows, the device enters dpm and reduces the charge current. the default offset voltage is 1.28 v below the no-load vbus voltage. the dc offset is 3.2 v (0000000). figure 31. inputvoltage register ( smbus address = 3dh) [reset = vbus-1.28v] 15 14 13 12 11 10 9 8 reserved input voltage, bit 7 input voltage, bit 6 input voltage, bit 5 input voltage, bit 4 input voltage, bit 3 input voltage, bit 2 r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 input voltage, bit 1 input voltage, bit 0 reserved r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 35. inputvoltage register (smbus address = 3dh) field descriptions smbus bit field type reset description 15-14 reserved r/w 00b not used. 1 = invalid write. 13 input voltage, bit 7 r/w 0b 0 = adds 0 mv of input voltage. 1 = adds 8192 mv of input voltage. 12 input voltage, bit 6 r/w 0b 0 = adds 0 mv of input voltage. 1 = adds 4096mv of input voltage. 11 input voltage, bit 5 r/w 0b 0 = adds 0 mv of input voltage. 1 = adds 2048 mv of input voltage. 10 input voltage, bit 4 r/w 0b 0 = adds 0 mv of input voltage. 1 = adds 1024 mv of input voltage. 9 input voltage, bit 3 r/w 0b 0 = adds 0 mv of input voltage. 1 = adds 512 mv of input voltage. 8 input voltage, bit 2 r/w 0b 0 = adds 0 mv of input voltage. 1 = adds 256 mv of input voltage. table 36. inputvoltage register (smbus address = 3dh) field descriptions smbus bit field type reset description 7 input voltage, bit 1 r/w 0b 0 = adds 0 mv of input voltage. 1 = adds 128 mv of input voltage. 6 input voltage, bit 0 r/w 0b 0 = adds 0 mv of input voltage. 1 = adds 64 mv of input voltage 5-0 reserved r/w 000000b not used. value ignored.
61 BQ25710 www.ti.com slusd20 ? july 2018 product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.6.7 otgvoltage register ( smbus address = 3bh) [reset = 0h] to set the otg output voltage limit, write to reg0x 3b() using the data format listed in figure 32 , table 37 , and table 38 . the dac is clamped in digital core at minimal 3v and maximum 20.8v. any register writing lower than the minimal or higher than the maximum will be ignored. when reg0x 32[2] = 1, there is no dac offset. when reg0x 32[2] = 0 the dac is offset by 1.28v figure 32. otgvoltage register ( smbus address = 3bh) [reset = 0h] 15 14 13 12 11 10 9 8 reserved otg voltage, bit 11 otg voltage, bit 10 otg voltage, bit 9 otg voltage, bit 8 otg voltage, bit 7 otg voltage, bit 6 r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 otg voltage, bit 5 otg voltage, bit 4 otg voltage, bit 3 otg voltage, bit 2 otg voltage, bit 1 otg voltage, bit 0 reserved r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 37. otgvoltage register (smbus address = 3bh) field descriptions smbus bit field type reset description 15-14 reserved r/w 00b not used. 1 = invalid write. 13 otg voltage, bit 11 r/w 0b 0 = adds 0 mv of otg voltage. 1 = adds 16656 mv of otg voltage. 12 otg voltage, bit 10 r/w 0b 0 = adds 0 mv of otg voltage. 1 = adds 8328 mv of otg voltage. 11 otg voltage, bit 9 r/w 0b 0 = adds 0 mv of otg voltage. 1 = adds 4164 mv of otg voltage. 10 otg voltage, bit 8 r/w 0b 0 = adds 0 mv of otg voltage. 1 = adds 2082 mv of otg voltage. 9 otg voltage, bit 7 r/w 0b 0 = adds 0 mv of otg voltage. 1 = adds 1041 mv of otg voltage. 8 otg voltage, bit 6 r/w 0b 0 = adds 0 mv of otg voltage. 1 = adds 521 mv of otg voltage. table 38. otgvoltage register (smbus address = 3bh) field descriptions smbus bit field type reset description 7 otg voltage, bit 5 r/w 0b 0 = adds 0 mv of otg voltage. 1 = adds 260 mv of otg voltage. 6 otg voltage, bit 4 r/w 0b 0 = adds 0 mv of otg voltage. 1 = adds 130 mv of otg voltage. 5 otg voltage, bit 3 r/w 0b 0 = adds 0 mv of otg voltage. 1 = adds 65 mv of otg voltage. 4 otg voltage, bit 2 r/w 0b 0 = adds 0 mv of otg voltage. 1 = adds 33 mv of otg voltage. 3 otg voltage, bit 1 r/w 0b 0 = adds 0 mv of otg voltage. 1 = adds 16 mv of otg voltage. 2 otg voltage, bit 0 r/w 0b 0 = adds 0 mv of otg voltage. 1 = adds 8.1 mv of otg voltage.
62 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated table 38. otgvoltage register (smbus address = 3bh) field descriptions (continued) smbus bit field type reset description 1-0 reserved r/w 00b not used. value ignored.
63 BQ25710 www.ti.com slusd20 ? july 2018 product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.6.8 otgcurrent register ( smbus address = 3ch) [reset = 0000h] to set the otg output current limit, write to reg0x 3c() using the data format listed in figure 33 , table 39 , and table 40 . figure 33. otgcurrent register ( smbus address = 3ch) [reset = 0000h] 15 14 13 12 11 10 9 8 reserved otg current set by host, bit 6 otg current set by host, bit 5 otg current set by host, bit 4 otg current set by host, bit 3 otg current set by host, bit 2 otg current set by host, bit 1 otg current set by host, bit 0 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 reserved r/w legend: r/w = read/write; r = read only; -n = value after reset table 39. otgcurrent register (smbus address = 3ch) field descriptions smbus bit field type reset description 15 reserved r/w 0b not used. 1 = invalid write. 14 otg current set by host, bit 6 r/w 0b 0 = adds 0 ma of otg current. 1 = adds 3200 ma of otg current. 13 otg current set by host, bit 5 r/w 0b 0 = adds 0 ma of otg current. 1 = adds 1600ma of otg current. 12 otg current set by host, bit 4 r/w 0b 0 = adds 0 ma of otg current. 1 = adds 800 ma of otg current. 11 otg current set by host, bit 3 r/w 0b 0 = adds 0 ma of otg current. 1 = adds 400 ma of otg current. 10 otg current set by host, bit 2 r/w 0b 0 = adds 0 ma of otg current. 1 = adds 200 ma of otg current. 9 otg current set by host, bit 1 r/w 0b 0 = adds 0 ma of otg current. 1 = adds 100 ma of otg current. 8 otg current set by host, bit 0 r/w 0b 0 = adds 0 ma of otg current. 1 = adds 50 ma of otg current. table 40. otgcurrent register (smbus address = 3ch) field descriptions smbus bit field type reset description 7-0 reserved r/w 00000000 b not used. value ignored.
64 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.6.9 adcvbus/psys register ( smbus address = 23h) ? psys: full range: 3.06 v, lsb: 12 mv ? vbus: full range: 3200 mv to 19520 mv, lsb: 64 mv figure 34. adcvbus/psys register ( smbus address = 23h) 15 14 13 12 11 10 9 8 r r r r r r r r 7 6 5 4 3 2 1 0 r r r r r r r r legend: r/w = read/write; r = read only; -n = value after reset table 41. adcvbus/psys register field descriptions bit field type reset description 15-8 r 8-bit digital output of input voltage 7-0 r 8-bit digital output of system power
65 BQ25710 www.ti.com slusd20 ? july 2018 product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.6.10 adcibat register ( smbus address = 24h) ? ichg: full range: 8.128 a, lsb: 64 ma ? idchg: full range: 32.512 a, lsb: 256 ma figure 35. adcibat register ( smbus address = 24h) 15 14 13 12 11 10 9 8 reserved r r r r r r r 7 6 5 4 3 2 1 0 reserved r r r r r r r legend: r/w = read/write; r = read only; -n = value after reset table 42. adcibat register field descriptions bit field type reset description 15 reserved r not used. value ignored. 14-8 r 7-bit digital output of battery charge current 7 reserved r not used. value ignored. 6-0 r 7-bit digital output of battery discharge current
66 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.6.11 adciincmpin register ( smbus address = 25h) ? iin: full range: 12.75 a, lsb: 50 ma ? cmpin: full range: 3.06 v, lsb: 12 mv figure 36. adciincmpin register ( smbus address = 25h) 15 14 13 12 11 10 9 8 r r r r r r r r 7 6 5 4 3 2 1 0 r r r r r r r r legend: r/w = read/write; r = read only; -n = value after reset table 43. adciincmpin register field descriptions bit field type reset description 15-8 r 8-bit digital output of input current 7-0 r 8-bit digital output of cmpin voltage
67 BQ25710 www.ti.com slusd20 ? july 2018 product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.6.12 adcvsysvbat register ( smbus address = 26h) ? vsys: full range: 2.88 v to 19.2 v, lsb: 64 mv ? vbat: full range: 2.88 v to 19.2 v, lsb: 64 mv figure 37. adcvsysvbat register ( smbus address = 26h) (reset = ) 15 14 13 12 11 10 9 8 r r r r r r r r 7 6 5 4 3 2 1 0 r r r r r r r r legend: r/w = read/write; r = read only; -n = value after reset table 44. adcvsysvbat register field descriptions bit field type reset description 15-8 r 8-bit digital output of system voltage 7-0 r 8-bit digital output of battery voltage
68 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.6.13 id registers 9.6.13.1 manufactureid register ( smbus address = feh) [reset = 0040h] figure 38. manufactureid register ( smbus address = feh) [reset = 0040h] 15-0 manufacture_id r legend: r/w = read/write; r = read only; -n = value after reset table 45. manufactureid register field descriptions smbus bit field type reset description (read only) 15-0 manufacture_id r 40h 9.6.13.2 device id (deviceaddress) register ( smbus address = ffh) [reset = 0h] figure 39. device id (deviceaddress) register ( smbus address = ffh) [reset = 0h] 15-8 reserved r 7-0 device_id r legend: r/w = read/write; r = read only; -n = value after reset table 46. device id (deviceaddress) register field descriptions smbus bit field type reset description (read only) 15-8 reserved r 0b reserved 7-0 device_id r 0b smbus: 89h
69 BQ25710 www.ti.com slusd20 ? july 2018 product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) refer to adapter specification for settings for input voltage and input current limit. (2) refer to battery specification for settings. 10 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 10.1 application information the bq2571xevm-017 evaluation module (evm) is a complete charger module for evaluating the BQ25710. the application curves were taken using the bq2571xevm-017. refer to the evm user's guide ( sluubt8 ) for evm information. 10.2 typical application figure 40. application diagram 10.2.1 design requirements design parameter example value input voltage (1) 3.5 v < adapter voltage < 24 v input current limit (1) 3.2 a for 65 w adapter battery charge voltage (2) 8400 mv for 2s battery battery charge current (2) 3072 ma for 2s battery BQ25710 acn vbus hidrv1 srn iadpt ibat psys adapter vsys batt btst1 btst2 lodrv1 sw1 sw2 lodrv2 hidrv2 srp batdrv vdda comp1 comp2 sda scl 3.3v or 1.8v chrg_ok cell_batpresz 1.05v prochot acp sys host (smbus) q1 q2 q3 q4 regn gnd ilim_hiz en_otg r ac =10m : 2.2 3.3uf 1uf regn 10 : 50 : 10k : 10k : 10k : 100pf 100pf 30k : vdda 250k : 350k : to cpu 47nf 47nf 6x10 p f : 1 p f 6x10 p f optional snubber 10k : cmpout cmpin r sr =10m : 10nf 2.2uh 100k : 1 : 470nf 15nf 15nf 10 : 10 :
70 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated typical application (continued) design parameter example value minimum system voltage (2) 6144 mv for 2s battery 10.2.2 detailed design procedure the parameters are configurable using the evaluation software. the simplified application circuit (see figure 40 , as the application diagram) shows the minimum component requirements. inductor, capacitor, and mosfet selection are explained in the rest of this section. refer to the evm user's guide ( sluubt8 ) for the complete application schematic. 10.2.2.1 acp-acn input filter the BQ25710 has average current mode control. the input current sensing through acp/acn is critical to recover inductor current ripple. parasitic inductance on board will generate high frequency ringing on acp-acn which overwhelms converter sensed inductor current information, so it is difficult to manage parasitic inductance created based on different pcb layout. bigger parasitic inductance will generate bigger sense current ringing which will cause the average current control loop to go into oscillation. for real system board condition, we suggest to use below circuit design to get best result and filter noise induced from different pcb parasitic factor. with time constant of filter from 47 nsec to 200 nsec, the filtering on ringing is effective and in the meantime, the delay of on the sensed signal is small and therefore poses no concern for average current mode control. figure 41. acn-acp input filter 10.2.2.2 inductor selection the BQ25710 has two selectable fixed switching frequency. higher switching frequency allows the use of smaller inductor and capacitor values. inductor saturation current should be higher than the charging current (i chg ) plus half the ripple current (i ripple ): (3) the inductor ripple current in buck operation depends on input voltage (v in ), duty cycle (d buck = v out /v in ), switching frequency (f s ) and inductance (l): (4) during boost operation, the duty cycle is: d boost = 1 ? (v in /v bat ) and the ripple current is: the maximum inductor ripple current happens with d = 0.5 or close to 0.5. for example, the battery charging voltage range is from 9 v to 12.6 v for 3-cell battery pack. for 20-v adapter voltage, 10-v battery voltage gives the maximum inductor ripple current. another example is 4-cell battery, the battery voltage range is from 12 v to 16.8 v, and 12-v battery voltage gives the maximum inductor ripple current. in ripple_buck s v d (1 d) i = l - f sat chg ripple i i + (1/2) i 3 rac acp acn r acp 10ohm r acn 10ohm c acp 15nf c acn 15nf BQ25710 c diff open 4~6x10uf (0805) 1nf+10nf (0402) hidrv1 q1
71 BQ25710 www.ti.com slusd20 ? july 2018 product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated usually inductor ripple is designed in the range of (20 ? 40%) maximum charging current as a trade-off between inductor size and efficiency for a practical design. 10.2.2.3 input capacitor input capacitor should have enough ripple current rating to absorb input switching ripple current. the worst case rms ripple current is half of the charging current when duty cycle is 0.5 in buck mode. if the converter does not operate at 50% duty cycle, then the worst case capacitor rms current occurs where the duty cycle is closest to 50% and can be estimated by equation 5 : (5) low esr ceramic capacitor such as x7r or x5r is preferred for input decoupling capacitor and should be placed to the drain of the high side mosfet and source of the low side mosfet as close as possible. voltage rating of the capacitor must be higher than normal input voltage level. 25 v rating or higher capacitor is preferred for 19 v - 20 v input voltage. minimum 4 - 6 pcs of 10- f 0805 size capacitor is suggested for 45 - 65 w adapter design. ceramic capacitors show a dc-bias effect. this effect reduces the effective capacitance when a dc-bias voltage is applied across a ceramic capacitor, as on the input capacitor of a charger. the effect may lead to a significant capacitance drop, especially for high input voltages and small capacitor packages. see the manufacturer's datasheet about the performance with a dc bias voltage applied. it may be necessary to choose a higher voltage rating or nominal capacitance value in order to get the required value at the operating point. 10.2.2.4 output capacitor output capacitor also should have enough ripple current rating to absorb output switching ripple current. in buck mode the output capacitor rms current is given: to get good loop stability, the resonant frequency of the output inductor and output capacitor should be designed between 10 khz and 20 khz. the preferred ceramic capacitor is 25-v x7r or x5r for output capacitor. minimum 6 pcs of 10- f 0805 size capacitor is suggested to be placed by the inductor. place the capacitors after q4 drain. place minimum 10 f after the charge current sense resistor for best stability. ceramic capacitors show a dc-bias effect. this effect reduces the effective capacitance when a dc-bias voltage is applied across a ceramic capacitor, as on the output capacitor of a charger. the effect may lead to a significant capacitance drop, especially for high output voltages and small capacitor packages. see the manufacturer's data sheet about the performance with a dc bias voltage applied. it may be necessary to choose a higher voltage rating or nominal capacitance value in order to get the required value at the operating point. 10.2.2.5 power mosfets selection four external n-channel mosfets are used for a synchronous switching battery charger. the gate drivers are internally integrated into the ic with 6 v of gate drive voltage. 30 v or higher voltage rating mosfets are preferred for 19 v - 20 v input voltage. figure-of-merit (fom) is usually used for selecting proper mosfet based on a tradeoff between the conduction loss and switching loss. for the top side mosfet, fom is defined as the product of a mosfet's on-resistance, r ds(on) , and the gate-to-drain charge, q gd . for the bottom side mosfet, fom is defined as the product of the mosfet's on-resistance, r ds(on) , and the total gate charge, q g . fom top = r ds(on) x q gd ; fom bottom = r ds(on) x q g (6) the lower the fom value, the lower the total power loss. usually lower r ds(on) has higher cost with the same package size. the top-side mosfet loss includes conduction loss and switching loss. it is a function of duty cycle (d=v out /v in ), charging current (i chg ), mosfet's on-resistance (r ds(on) ), input voltage (v in ), switching frequency (f s ), turn on time (t on ) and turn off time (t off ): (7) the first item represents the conduction loss. usually mosfet r ds(on) increases by 50% with 100 c junction temperature rise. the second term represents the switching loss. the mosfet turn-on and turn-off times are given by: 2 top chg ds(on) in chg on off s 1 p = d i r + v i (t + t ) 2 f cin chg i = i d (1 d) -
72 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated (8) where q sw is the switching charge, i on is the turn-on gate driving current and i off is the turn-off gate driving current. if the switching charge is not given in mosfet datasheet, it can be estimated by gate-to-drain charge (q gd ) and gate-to-source charge (q gs ): (9) gate driving current can be estimated by regn voltage (v regn ), mosfet plateau voltage (v plt ), total turn-on gate resistance (r on ) and turn-off gate resistance (r off ) of the gate driver: (10) the conduction loss of the bottom-side mosfet is calculated with the following equation when it operates in synchronous continuous conduction mode: p bottom = (1 - d) x i chg 2 x r ds(on) (11) when charger operates in non-synchronous mode, the bottom-side mosfet is off. as a result all the freewheeling current goes through the body-diode of the bottom-side mosfet. the body diode power loss depends on its forward voltage drop (v f ), non-synchronous mode charging current (i nonsync ), and duty cycle (d). p d = v f x i nonsync x (1 - d) (12) the maximum charging current in non-synchronous mode can be up to 0.25 a for a 10-m charging current sensing resistor or 0.5 a if battery voltage is below 2.5 v. the minimum duty cycle happens at lowest battery voltage. choose the bottom-side mosfet with either an internal schottky or body diode capable of carrying the maximum non-synchronous mode charging current. 10.2.3 application curves 2-cell without battery figure 42. power up from 20 v 2-cell without battery figure 43. power up from 5 v sw sw on off on off q q t = , t = i i sw gd gs 1 q = q + q 2 regn plt plt on off on off v - v v i = , i = r r ch1: vbus ch2: vdda ch3: chrg_ok ch4: vsys ch1: vbus ch2: vdda ch3: chrg_ok ch4: vsys
73 BQ25710 www.ti.com slusd20 ? july 2018 product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated 3-cell vbat = 10 v figure 44. power off from 12 v vbus 5 v to 20 v figure 45. system regulation vbus = 20 v, vsys = 10 v, isys = 200 ma figure 46. pfm operation figure 47. pwm operation vbus = 5 v, vbat = 10 v figure 48. switching during boost mode vbus = 12 v, vbat = 12 v figure 49. switching during buck boost mode ch1: hidrv2 ch2: sw2 ch3: lodrv2 ch4: il ch2: sw1 ch3: sw2 ch4: il ch1: vbus ch2: sw1 ch3: sw2 ch4: il ch1: vbus ch2: sw1 ch3: sw2 ch4: vsys with 9vos ch2: sw1 ch3: sw2 ch4: il ch1: hidrv1 ch2: sw1 ch3: lodrv1 ch1: il
74 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated vbus = 12 v/3.3 a, 3-cell, vsys = 9 v, without battery figure 50. system regulation in buck mode vbus = 9 v/3.3 a, 3-cell, vsys = 9 v, without battery figure 51. system regulation in buck boost mode vbus = 5 v/3.3 a, 3-cell, vsys = 9 v, without battery figure 52. system regulation in boost mode vbus = 20 v/3.3 v, vbat = 7.5 v figure 53. input current regulation in buck mode vbus = 5 v/3.3 v, vbat = 7.5 v figure 54. input current in boost mode vbus = 5 v figure 55. otg power up from 8 v battery ch2: iin ch3: isys ch4: ibat ch1: vsys ch2: iin ch3: isys ch1: vsys ch2: iin ch3: isys ch1: en_otg ch2: vbus ch2:iin ch3:isys ch4:ibat ch1: vsys ch2: iin ch3: isys
75 BQ25710 www.ti.com slusd20 ? july 2018 product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated vbat = 10 v, vbus 5 v to 20 v, iotg = 500 ma figure 56. otg voltage ramp up figure 57. otg power off vbat = 10 v, vbus = 20 v figure 58. otg load transient ch1: scl ch2: vbus ch3: sw2 ch1: scl ch2: vbus ch3: sw2 ch2: vbus ch3: ivbus
76 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated 11 power supply recommendations the valid adapter range is from 3.5 v ( v vbus_conven ) to 24 v (acov) with at least 500-ma current rating. when chrg_ok goes high, the system is powered from adapter through the charger. when adapter is removed, the system is connected to battery through batfet. typically the battery depletion threshold should be greater than the minimum system voltage so that the battery capacity can be fully utilized for maximum battery life.
77 BQ25710 www.ti.com slusd20 ? july 2018 product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated 12 layout 12.1 layout guidelines the switching node rise and fall times should be minimized for minimum switching loss. proper layout of the components to minimize high frequency current path loop (see layout example section) is important to prevent electrical and magnetic field radiation and high frequency resonant problems. here is a pcb layout priority list for proper layout. layout pcb according to this specific order is essential. 1. place the input capacitor as close as possible to the supply of the switching mosfet and ground connections. use a short copper trace connection. these parts must be placed on the same layer of pcb using vias to make this connection. 2. the device must be placed close to the gate pins of the switching mosfet. keep the gate drive signal traces short for a clean mosfet drive. the device can be placed on the other side of the pcb of switching mosfets. 3. place an inductor input pin as close as possible to the output pin of the switching mosfet. minimize the copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the charging current. do not use multiple layers in parallel for this connection. minimize parasitic capacitance from this area to any other trace or plane. 4. the charging current sensing resistor should be placed right next to the inductor output. route the sense leads connected across the sensing resistor back to the device in same layer, close to each other (minimize loop area) and do not route the sense leads through a high-current path (see figure 60 for kelvin connection for best current accuracy). place a decoupling capacitor on these traces next to the device. 5. place an output capacitor next to the sensing resistor output and ground. 6. output capacitor ground connections must be tied to the same copper that connects to the input capacitor ground before connecting to system ground. 7. use a single ground connection to tie the charger power ground to the charger analog ground. just beneath the device, use analog ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling. 8. route analog ground separately from power ground. connect analog ground and connect power ground separately. connect analog ground and power ground together using power pad as the single ground connection point. or using a 0- resistor to tie analog ground to power ground (power pad should tie to analog ground in this case if possible). 9. decoupling capacitors must be placed next to the device pins. make trace connection as short as possible. 10. it is critical that the exposed power pad on the backside of the device package be soldered to the pcb ground. 11. the via size and number should be enough for a given current path. see the evm design ( sluubt8 ) for the recommended component placement with trace and via locations. for wqfn information, see slua271 . 12.2 layout example 12.2.1 layout consideration of current path figure 59. high frequency current path high frequency current path l1 r1 c2 c1 gnd phase v bat bat v in
78 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated layout example (continued) 12.2.2 layout consideration of short circuit protection figure 60. sensing resistor pcb layout charge current direction to srp and srn pin r sns to inductor to capacitor and battery current sensing direction
79 BQ25710 www.ti.com slusd20 ? july 2018 product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated 13 device and documentation support 13.1 device support 13.1.1 third-party products disclaimer ti's publication of information regarding third-party products or services does not constitute an endorsement regarding the suitability of such products or services or a warranty, representation or endorsement of such products or services, either alone or in combination with any ti product or service. 13.2 documentation support 13.2.1 related documentation for related documentation see the following: ? semiconductor and ic package thermal metrics application report spra953 ? bq2571x evaluation module user's guide sluubt8 ? qfn/son pcb attachment application report slua271 13.3 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 13.4 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 13.5 trademarks e2e is a trademark of texas instruments. 13.6 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 13.7 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions.
80 BQ25710 slusd20 ? july 2018 www.ti.com product folder links: BQ25710 submit documentation feedback copyright ? 2018, texas instruments incorporated 14 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 20-jul-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples BQ25710rsnr active qfn rsn 32 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 BQ25710 BQ25710rsnt active qfn rsn 32 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 BQ25710 a0 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
package option addendum www.ti.com 20-jul-2018 addendum-page 2
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant BQ25710rsnr qfn rsn 32 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 q2 BQ25710rsnt qfn rsn 32 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 q2 package materials information www.ti.com 19-jul-2018 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) BQ25710rsnr qfn rsn 32 3000 367.0 367.0 35.0 BQ25710rsnt qfn rsn 32 250 210.0 185.0 35.0 package materials information www.ti.com 19-jul-2018 pack materials-page 2

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